標題: 請問由Verilog code到IC layout 需要哪些軟體 [打印本頁] 作者: leesg 時間: 2009-5-18 03:38 PM 標題: 請問由Verilog code到IC layout 需要哪些軟體 問題, 已完成 Verilog code 設計, 模擬(ModelSim)! `! \5 n J6 B
想要用軟體直接 run 到 IC Layout 產生 die photo, % f! a5 |: K3 s$ Q0 w m要用什麼軟體組合 ? (輸入 verilog code, 自動跑出 IC Layout) $ t; B' z) d9 U! i1. 8 i" U8 k7 Q# `- Tdesign compiler + Astro ?# \2 M1 O0 Y; R5 V6 Q' A
: p$ ]1 @. `7 w* O# h% u2. ! f' ?+ H1 ], G' R. D. Csynopsys IC compiler ? + b' S8 ~* X9 P : v; R* h3 c' p3. 4 n" R7 H; {2 I8 F6 w" D1 l
cadnece virtuso ?作者: lee100 時間: 2009-5-19 10:30 AM
Synopsys R2G flow t; v9 _8 U! z; \+ I; ~$ M1. rtl simulation by vcs0 i* S0 y- O2 E* D# ~4 E: E
2. synthesis by design compiler ultra with dc/dct mode+ W( k$ V- W$ z$ M# p& W7 k2 u& X) U
3. dft insertion by dft compiler$ I7 Y1 Y5 P% X ~: M+ _' A
4. jtag insertion by bsd compiler+ _0 ?3 P# k/ \; Z9 u: K( Q2 B
5. ICG insertion by power compiler A- r) E; D& M& B6. pre/post-layout STA by prime time( X! `4 t0 L7 p+ R; `$ g
7. pre/post-layout power analysis by prime time px5 c }# l; H* k5 _, N% j
8. PnR by IC compiler: I& j' Y& {/ E1 e' |; f
9. post-layout SI analysis by prime time si ( }8 G9 t( I" T10. post-layout simulation by vcs作者: putechen 時間: 2009-9-7 11:32 AM
sometimes ,star-RCXT is necessary.just for layout PEX.作者: yytseng 時間: 2009-9-28 09:44 PM
after above place and route task, you need virtuoso or laker to merge cell layouts and do some editing.* }5 B; u. M" \) }, l9 ~- ], m5 U
clean up LVS/DRC/ERC/ESD violations with calibre or (hercules, assura) tools.作者: ejean 時間: 2009-10-9 05:16 PM
1. magma is another solution( [; [* l2 E8 [7 ~. W, L5 B
2. Astro from synopsys 0 Y! G6 f- Z' [7 H8 b3. FirstEncounter from Cadence - P9 O# l$ F7 h. I1 y# O$ H7 Y) q2 `: P
All with basic DRC and LVS, you have to run Calibre, etc. to finish the final verification.作者: ilovepachaya 時間: 2010-9-16 09:18 AM
私心推薦APR使用IC Compiler 效果很好