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標題:
Calibration techniques in nyquist AD converters
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作者:
cnasic
時間:
2008-3-11 11:50 AM
標題:
Calibration techniques in nyquist AD converters
Table of contents
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List of abbreviations
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List of symbols
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Preface
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1 Introduction 1
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1.1 A/Dconversion systems . . . . . . . . . . . . . . . . . . . . . . 1
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1.2 Motivation and objectives . . . . . . . . . . . . . . . . . . . . . . 5
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1.3 Layout of the book . . . . . . . . . . . . . . . . . . . . . . . . . 5
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2 Accuracy, speed and power relation 7
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2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
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2.2 IC-technology accuracy limitations . . . . . . . . . . . . . . . . . 8
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2.2.1 Process mismatch . . . . . . . . . . . . . . . . . . . . . . 8
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2.2.2
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2.2.3 Matching versus noise requirements . . . . . . . . . . . . 11
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2.3 Speed and power . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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2.4 Maximumspeed . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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2.5 . . . . . . . . . . . . . . . . . . . . . 15
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2.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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3 A/D converter architecture comparison 21
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3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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3.2 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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3.2.1 Fullflash . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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3.2.2 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . 26
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3.2.3 Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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3.3 Folding and interpolation . . . . . . . . . . . . . . . . . . . . . . 33
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3.4 Two-step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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Thermal noise . . . . . . . . . . . . . . . . . . . . . . . 10
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CMOS technology trends
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Table of contents
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3.5 Pipe-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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3.6 Successive approximation . . . . . . . . . . . . . . . . . . . . . . 54
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3.7 Theoretical power consumption comparison . . . . . . . . . . . . 56
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3.7.1 Figure-of-Merit (FoM) . . . . . . . . . . . . . . . . . . . 57
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3.7.2 Architecture comparison as a function of the resolution . . 57
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3.7.3 Architecture comparison as a function of the sampling speed 65
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3.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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4 Enhancement techniques for two-step A/D converters 67
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4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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4.2 Error sources ina two-step architecture . . . . . . . . . . . . . . 67
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4.3 Residue gain in two-stepA/Dconverters . . . . . . . . . . . . . . 69
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4.3.1 Single-residue signal processing . . . . . . . . . . . . . . 69
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4.3.2 Dual-residue signal processing . . . . . . . . . . . . . . . 71
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4.3.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 75
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4.4 Offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . 75
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4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 75
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4.4.2 Calibration overview . . . . . . . . . . . . . . . . . . . . 75
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4.4.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 82
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4.5 Mixed-signal chopping and calibration . . . . . . . . . . . . . . . 83
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4.5.1 Residue amplifier offset chopping . . . . . . . . . . . . . 83
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4.5.2 Offset extraction fromdigital output . . . . . . . . . . . . 84
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4.5.3 Pseudo random chopping . . . . . . . . . . . . . . . . . . 88
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4.5.4 Offset extraction and analog compensation . . . . . . . . 91
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4.5.5 Offset extraction in a dual-residue two-step converter . . . 93
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4.5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 102
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5 A 10-bit two-step ADC with analog online calibration 103
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5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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5.2
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5.2.1 Coarse quantizer accuracy . . . . . . . . . . . . . . . . . 106
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5.2.2 D/A converter and subtractor accuracy . . . . . . . . . . . 107
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5.2.3 Coarse andfineA/Dconverter references . . . . . . . . . 108
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5.2.4 Amplifier gain and offset accuracy . . . . . . . . . . . . . 109
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5.3 Circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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5.3.1 Track-and-hold circuit . . . . . . . . . . . . . . . . . . . 111
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5.3.2 CoarseA/D,D/Aconverter and subtractor . . . . . . . . . 111
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5.3.3 Coarse ladder requirements . . . . . . . . . . . . . . . . . 112
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5.3.4 Offset compensated residue amplifier . . . . . . . . . . . 113
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5.3.5 FineA/Dconverter . . . . . . . . . . . . . . . . . . . . . 114
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5.3.6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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Two-Steparchitecture . . . . . . . . . . . . . . . . . . . . . . . 105
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Table of contents
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5.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . 117
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5.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
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5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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6 A 12-bit two-step ADC with mixed-signal chopping and calibration 123
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7 A low-power 16-bit three-step ADC for imaging applications 149
作者:
xp212125o
時間:
2010-4-16 02:27 AM
感謝分享
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先下載來看看
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thank you very much~
作者:
tuza2000
時間:
2011-9-19 08:06 AM
good material !!!
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