layout 的NMOS bulk端如何在LVS分開?

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I agree with 12345,
/ r. {, [- n$ `% V' {" Y2 Ybut I don't think that everyone can understand the rule file format.
) L- ~2 J4 a. F7 z4 T- ?: pIn my point of view,the layouter should know  what process(NWELL,Twin WELL,Triple WELL ...),Cross section ,what purpose of each layer and so on.(of course in the end,you have to understand the rule format)
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The lvs report suggested "Use LVS REPORT OPTION S" then you will get one more report.
It will be show what problem is.

Good luck.