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LOAD SDC FILE時
; ~! o" e6 v& |1 DAstro 訊息; [6 c% C# n9 y& ]; V" [1 ?& i
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~5 I8 ^) j7 y- y2 P; [" TInfo: starting Tcl processing, n# x4 z% ~( ~- _- }. X
Info: building design object name tables
X" V" v6 @6 _1 sWarning: No pins matched 'TOP/test/mul/A[26]' (SEL-004)
9 E8 Z# h+ @' yWarning: No pins matched 'TOP/test/mul/A[25]' (SEL-004)7 a' {; ?* w; O7 `' p" N
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; n% d" ~+ g# BSDC FILE
% F5 X- f; W$ \- z' ^3 u: z/ V+ D) G+ ]. J" ?: I
set_multicycle_path 9 -through [list [get_pins \# K9 G$ p) g9 A8 o7 z
{TOP/test/mul/A[26]}] [get_pins \. D: a) B- R' T7 J5 `5 D1 p
{TOP/test/mul/A[25]}] [get_pins \
6 F5 h+ H7 Q9 D5 J3 c6 G' R* e5 A3 k: O0 X6 J5 x* L, e) M
P4 ?3 @' P+ C7 y% A7 L3 T
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Verilog File
! l4 J1 b; z; j! W
) T" v+ _! y A! K& | uniquify_mul_0 mul ( .A(icwAeYfSum[26:0]), .B(
+ J" }0 C! c/ W @ A: [ icwAeYfNum[18:0]), .C(ae_avg) ); |
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