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Manager/Sr. Manager, wireless communication }0 g8 L* L( F4 o) P$ P
公 司:a leading developer of advanced digital imaging solution
- h" {9 r; }: |$ _1 j工作地点:上海
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; n6 \* w5 s5 G, f2 f0 ^职位描述
0 w, I" b5 v& tThis is a high visibility position at XX Technology (Shanghai). This position will lead a wireless design team to deliver products to address wireless emerging markets. The candidate will be responsible for developing communication system architecture and driving wireless R&D resources to deliver high cost/performance products. A successful candidate should have strong industrial experience in designing digital receivers/transmitters, and have in-depth knowledge of characteristics of wireless communication systems. The candidate is required not only to lead ASIC design team on design implementation and verification, but also to have the ability to communicate with other teams of various backgrounds, such as RF IC design, software and marketing in order to develop the best architecture for cost/performance tradeoff. The position also bears the responsibility of working with marketing and system teams for product definition, performance analysis and optimization.
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; O Q$ f9 o! f. PRequirements 9 Z1 G6 }& f% x( `- O% U' u
--- MSEE with 8+ years experience (5+ years for PhD) in communication SoC design, such as Bluetooth, Wi-Fi or DVB-C/S/H. " N S* H" I" ~& J* {; l
--- Direct design experience on modulation such as QPSk/QAM, DQPSK/8DPSK, OFDM, etc. and related channel encoding/decoding algorithms.4 q" Q2 W J) K# g: L
--- Good knowledge in communication related algorithms, such as AGC, carrier recovery, timing recovery, channel estimation and equalization.
$ F) w/ K! }. f- m c) ~1 [--- Strong knowledge in Wi-Fi (802.11 b/g) and/or Bluetooth is a must. Knowledge of rake receiver, MINO is a big plus , J% P# s; X) L0 |; \
--- Good experience in cost-driven architectural design, system partition and performance analysis is highly desirable # Z6 q* @8 k, D
--- Must have extensive SoC experience from design specification to netlist
! x0 P& g* c: I--- Supervising engineers and conducting chip/prototype (with FPGA) debugging in the lab environment
" Y: y8 k) K* ?0 M9 v" ?7 s( W--- Excellent hands-on experience in system bring-up and trouble-shooting in the lab environment is highly desirable
. R t ^" T4 p0 T! a# n--- Good experience and understanding of issues related to board level design, grounding, supply decoupling, filtering, spurs sources, etc. is a big plus. w. E# M3 M' ]3 a h* R3 i1 _( w
--- Self-motivated, excellent communication skills and ability to excel in a team environment |
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