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做fpga的前途問題

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1#
發表於 2013-8-16 13:37:50 | 顯示全部樓層
Senior Applications Engineer – Processors  m; d3 ^# U8 A* {( x, j- Z
. \$ z0 }! B! D9 Q5 a
公      司:A famous IC company
/ z% b; y; r3 Z( T" J工作地点:上海# N. J+ I% R. R. _
7 G+ `4 ~0 V& H3 G
Key Accountabilities
! G; G+ w2 S) H3 N% R4 g# z3 C' C/ LWork with ARM Processor design teams and Compute Subsystem teams to gain in-depth knowledge of our IPs, their micro-architecture and their application in an SoC design    `& i6 `+ p8 ^
Provide feedback to the IP design teams on potential product improvements & enhancements
$ c# F9 t/ I" ~Participate in big-LITTLE™ technology design projects and enablement activities  ! V4 w- m5 ]0 ?
Work with our Services Division to ensure that quality support and training is being deployed to the satisfaction of our lead partners
0 l0 g  ^5 Y" H% GPrepare and maintain material for lead partner support including training materials, white papers and application notes
% Z" |. T( X8 ~/ ^6 ^* \Work directly with lead partners delivering training, support and hands-on system design assistance to ensure that their goals are achieved. " }- G% o' A) B$ a- E/ d8 i# b- W  _

1 v7 n9 Y3 S$ q, t0 k- P; b" dEducation & Qualifications . T2 ^" T7 M! w( {
Qualified candidates will have a good university degree in Electronic Engineering, Computer Engineering or other relevant technical discipline.
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2#
發表於 2013-8-16 13:37:53 | 顯示全部樓層
Essential Technical / Professional Skills 1 E7 ^2 R$ T0 C9 X( j8 j% @
7-10 years of SoC design experience with strong understanding of microprocessors, ideally latest XX processor cores
( P9 \& P& {: k' L1 ?" G3 PKnowledge of various system IP blocks such as interconnect, memory controller, interrupt controller etc and experience in building a performance optimized design with necessary trade-off considerations $ z, A& B5 e# [1 h' }0 N
Experience or knowledge of FPGA or ASIC design, simulation and/or verification techniques, including RTL coding and simulation, in Verilog or VHDL$ _! }6 Z! i0 Q1 o3 h1 K1 Z
Understanding of FPGA or ASIC implementation flows (synthesis, scan insertion, layout)
- F8 }2 ]$ N& m9 p) U$ \) vA good understanding of the interaction between software and hardware
. P: J6 A/ x' v% a. J6 h! i1 pKnowledge of low power design methodologies
3 j" B, l9 L2 m% n( f0 ?; ]* u7 ^Experience of working closely with customers, providing technical support and training ) w+ f/ `: c; O8 Q/ Y
Ability to think under pressure, especially in front of customers and to provide logical and accurate problem analysis
- [8 M6 u# \) @" o0 hGood spoken and written English ; C/ R" ~1 b8 e+ Q4 i2 }
8 F, w; s4 }6 y* ^
Desirable Skills & Experience
: M- q( T- d# c7 l6 A* sExposure to multiple EDA tools for front-end design and simulation / i1 }% G5 W% ], y
Knowledge of XX technology, culture and the business model 3 m& \% H0 \+ z" d
Understanding of XX system architectures and end market applications ( y! l8 J5 F! `+ s; y. w; Y
Knowledge and experience in working with XX big-LITTLE™ technology.
1 T4 b, R, U2 |3 t9 v* E6 j) y0 I  r% b4 U& l# u
Personal Requirements
% a3 N) A' T: _3 eExcellent communication skills: listening, understanding and persuading  
& E% ]# X: K. d& ?' QHighly self-motivated with the ability to effectively work alone as well as in a team % u% |# P( \) c  x6 p% B
Must have the desire and ability to solve problems quickly. ; }, H8 _1 |! a$ q
Demonstrate a positive attitude and respect for all members of the team 3 ~1 M1 k2 a% W& z3 ?" O5 h' L5 s
Be motivated to continuously develop skills and accept a variety of responsibilities as part of contributing to the team’s success! e5 {) p1 I& u
Willingness to travel including US, UK, India and China, spending significant periods of time on customer sites and for learning trips.
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3#
發表於 2013-10-31 13:52:26 | 顯示全部樓層
Sr System Manager8 Y5 N3 J! y; r4 w

) L+ K, i1 a3 J" {$ X# y公      司:A famous IC company+ y4 z5 Q" |3 W6 X1 W6 h! p
工作地点:上海
5 E( W$ n6 K8 v( d- x9 d7 c# j
4 y  p+ W3 a* ?( |9 J8 M% CResponsibilities   
4 \  [4 q. v1 `7 T! ], z2 A! Z; p1.Manage a team with functions of FPGA-based design prototyping, pre/post-silicon validation, engineering/testing board development, ARM cortex-M processors based firmware development   * L) h" `3 ~; A8 [# X; n
2.Communicate to management, other functional teams and customers in an multi-site, international environment   
; x; y; _. j) e) c, X# G- D3.Hands-on knowledge in the system/board/firmware field and be able to help the team members  
5 p- H. Q$ m8 j9 d" ]5 [* i8 c6 ^4 u. y* V  ^: \- U
Mandatory Skills   
1 G& L+ o/ E( x" W/ Q' W1.        Fluency in English (both Oral and writing) and communication skill is essential for this position   
3 e: s8 z2 |! Z/ l2.        Good board design knowledge and experience in an IC engineering context   
& T& R  ]$ F$ d: m4 z! F* F4 K3.        FPGA based emulation system and flow   
" M# P7 g' Q7 Q( i, H- j3 b; r4.        Embedded system and firmware   . [! J. Z) H, U5 W& ~5 [
5.        Good understanding of computer interfaces and instrument control (USB, UART, GPIB etc)
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4#
發表於 2013-10-31 13:52:38 | 顯示全部樓層
Preferred Skills   
% I1 P6 f! C& g% p, b) [1.        Digital signal processing knowledge   
1 R, {+ {! l0 `- @5 t! _) A2.        Algorithm development   $ a  a" g* k# O$ i3 w3 P: j# k
3.        Product definition/Specification   ! _; l- ?" Y- Y2 J
4.        Analog/Mixed signal measurement and characterization   
) K/ D2 z; f( |4 ?+ |; q! Y5.        Smart meter design and application   5 n$ [5 G- U: Z, ^3 ^
  
  d  o0 Z$ L* q1 l! [# a* B/ M9 V' pEducation   # e% a- {' Q& P, ]- F
Master Degree of Electrical Engineering, Computer Science or Control system   0 z  \! P, k) ?- F4 x: [
  
; e6 U- }. }! U  F3 w' Q/ ~) BExperience  
& w8 v; N5 j& w! {6 p% j4 p1.10+ years of working experience in the high-tech industry.   3 j6 k6 P. B* E( y+ W. s# ~" r
2.At least 3 years of experience in an international company, or oversea working experience.   
, n( F2 H  a! d3 d7 E* _( l& K1 }3.At least 3 years of experience in a management or supervisor position   " r, \4 |+ f& |5 A# \
4.Experience in embedded system development   
; I$ O  W3 _' W5 k, I' o2 F5.Experience in system validation
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5#
發表於 2014-2-14 13:46:32 | 顯示全部樓層
Xilinx攜手Xylon推出logiADAK車載駕駛輔助系統套件 打造多達六個攝影機之系統設計
6 H, `8 L# [( m, C: K" x* F& VlogiADAK Zynq-7000 All Programmable SoC車載駕駛輔助套件包含特定應用軟體、參考設計及加速IP整合 / Y, u$ `- u: I& M) d  \+ Y: X

5 r  x3 D. N5 H, _# W1 f' p& ~  C  美商賽靈思(Xilinx, Inc.;NASDAQ:XLNX)與Xylon公司今天宣佈推出logiADAK Zynq®-7000 All Programmable SoC車載駕駛輔助套件。這款套件由賽靈思和Xylon、Embedded Vision Systems (eVS)及Digital Design Corporation (DDC)等產業合作夥伴共同研發,可讓汽車製造商和一線車載電子供應商擁有加速和簡化開發先進駕駛輔助系統 (ADAS)的能力,同時可讓系統擁有多達六個攝影機。賽靈思將於2月25至27日假德國紐倫堡舉辦的Embedded World大會展示logiADAK車載駕駛輔助套件,展示攤位編號為Stand 1-205。
, R$ p( Y7 U3 c' k& p( V
6 |8 n- N0 Z, z8 k% w2 ~8 ~# ?  加強功能後的車載駕駛輔助套件是一套可立即使用的開發平台,其中包含了特定應用軟體和完整的參考設計。這些參考設計可用作快速測試車輛安裝和展示作業,其客製化參考設計具備評估IP核心,以及為攝影機式ADAS打造的完整設計架構,可將更多客戶開發的軟體或IP型功能簡易地整合到系統中。
3 G$ P& j; v# ?; l1 E" m  {$ r! x- j
  以Xilinx® Zynq®-7000 All Programmable SoC為設計基礎的logiADAK平台可提供各種即時效能的功能,並能超越AEC-Q100認證條件以符合車載用途對溫度和品質的嚴峻要求。已通過完全資格驗證的Xilinx 汽車 (XA) Zynq-7000 All Programmable SoC產品,現已接受客戶訂單。
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6#
發表於 2014-2-14 13:47:13 | 顯示全部樓層
logiADAK車載駕駛輔助套件可加快開發的ADAS應用包括:4 `% k: i) i; s# o4 T" y. }
& s7 ~7 n3 d/ J- E* K6 k" I
·         採用多逹六個攝影機的360度全景3D和鳥瞰檢視模式,可加快更大型商用和特殊用途車輛之開發作業3 {- s& i: r' f9 Q+ ^. B
·         具備多種客製化檢視模式的後視攝影機,包括多個行人偵測指示器
- N- A( y* ]$ x, M5 x+ o0 w8 r·         偵測行人和車輛的前方防撞攝影機7 M5 u7 E* d3 D% t* S( i" n
·         車道偏離警示% ~" \& Z# z% s: c0 S) `; H
·         採用光學流演算的盲點偵測
8 L. v+ _* @6 T! f6 v: ^% ?( j4 ?; D# c: v7 L9 V) B
  賽靈思公司車用部門總監Nick DiFiore表示:「我們與車用產業體系的合作夥伴共同協助系統設計師快速、有效地開發具備多個攝影機的系統。可支援多達六個100萬像素攝影機的功能對較大型的車輛而言必不可缺,更遑論可在單一解決方案中結合全景式前方防撞攝影機或更多輔助功能對車載系統設計的重要性。」
: r# z1 b# I5 B, ?4 `
0 B) O0 }4 L: ?: A5 \5 X7 K  Xylon公司創辦人暨執行長Davor Kovačec表示:「這款以Xilinx Zynq-7000 All Programmable SoC為基礎並針對即時ADAS進行最佳化的開發平台,可讓汽車製造商及其電子零件供應商藉由這款高效能、可重新編程SoC整合他們自家的軟硬體IP,打造各種獨特並具差異化功能的駕駛輔助應用。」
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7#
發表於 2014-2-14 13:47:20 | 顯示全部樓層
 Zynq-7000 All Programmable SoC 緊密結合了內建ARM® dual-core Cortex™-A9 MPCore™處理系統的賽靈思領先業界的7系列FPGA技術,可快速開發高度整合、智慧型、最佳化和高靈活度的軟硬體ADAS。 " a3 d2 ^" P  `! e. O7 E) \3 n

7 U/ Y3 W4 n. M: Z+ `( ~) I0 e# [出貨時程; O& F1 o3 e/ k3 M8 @7 D- A
6 O# _( s9 x2 s& S; \' _
  logiADAK Zynq-7000 All Programmable SoC車載駕駛輔助套件現已由賽靈思聯盟計畫 (Xilinx Alliance Program)優質設計服務供應商夥伴Xylon提供
. G' ^2 I2 i3 Z& ^/ X  w5 D/ t1 v: ?& X- s
關於Xylon, F+ [3 j0 q+ O% x+ E) T
" M0 N1 |$ T6 r* H& l, S
  專注於各種FPGA設計的Xylon公司成立於1995年,同時也是嵌入式影像、影音和網路等領域的優異IP供應商。欲了解更多Xylon相關資訊,請瀏覽www.logicbricks.com網站。
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8#
發表於 2014-3-7 13:18:46 | 顯示全部樓層
FPGA应用开发工程师
; T) T( k2 V! ~" N公      司:A famous IC company5 ~7 K# |( t, Y
工作地点:上海7 E! u: l7 d3 f9 {3 m

; \, t7 z. V; H; T- U1 Z, V9 j& k职位描述: " k  O3 A2 g$ C7 v6 C
1、负责项目中FPGA 部分的方案设计,主要针对视频图像数据处理。
' k. w' Y7 A7 Y8 A* t' m2、负责FPGA选型及相关电路的设计和调试; ; z( b5 e  x/ J; o- R" [1 B* l
3、负责FPGA的代码编写和维护;
" @& h+ Y* F7 r4、负责FPGA的仿真和调试;
* q, n! ?6 A  U' |. i5、负责部分嵌入式软件开发工作。 9 r# M. b/ n# G% s( B& D

0 D' W( P2 i" y! }: ]任职要求:
6 r+ ]7 h' H; K+ S! s) D& X# u1、本科及以上学历,微电子、通信、计算机相关专业,具有两年以上的FPGA开发经验;
7 Y: E% C  g" `) J6 G- i2、精通Verilog语言和FPGA设计流程;
  h, P0 u, m0 f4 O3、有独立开发过FPGA模块或者项目的经验;
5 Y( r% G, ?6 X6 M- d4、能独立完成中型FPGA模块的设计,代码编写和后期仿真调试;
) t2 t/ W' ]3 f1 U5、有图像处理及图像增强的项目经验者优先; 0 k, E4 B" F/ ~+ e  |+ U3 W
6、有C/C++语言开发经验者优先。
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9#
發表於 2014-7-16 08:22:32 | 顯示全部樓層
Digital Design Engineer
4 I3 I3 k6 @+ t+ g7 @
2 L! z+ M9 m5 ~公      司:A famous IC company
2 C& m1 c$ L8 ~& S* T7 s工作地点:上海
! o: y" V: t, R% _& Y; D" C% S% L. a- v7 f8 [5 n
Duties
9 C, g6 t. q  A- ~! W5 @, JWork with internal and external customers to understand product requirements.
# m- v) a7 p/ t; i2 |) P7 LCreate critical silicon technologies to meet the product requirements. 0 s, U, O; E( z# v: k$ x: b
Work out critical design flows and methodologies to execute implementation flawlessly.
5 Q+ w! l0 _6 O' R7 }  P! N+ H, GDesign and deliver final design through multiple stages like specification, micro-architecture, IP  development, RTL coding, verification, logic synthesis, DFT, timing convergence, as well as helping on physical implementation.
8 \4 x  ]5 q7 y1 r4 oComplete full documentation. ' @& G; P0 U2 w9 Q
Help and mentor junior engineers.
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10#
發表於 2014-7-16 08:22:35 | 顯示全部樓層
Job Requirements:  " g7 _$ m" o& L4 a0 D
Solid understanding of all SoC chip development stages is required.  
2 m  i4 L9 T; \9 d3 @# \9 W" GHands-on Experience with complex SoC design flow is required.  
' V4 e9 T3 \$ ^% T3 O/ d+ NHands-on Experience with RTL coding, simulation, verification is required. * M2 d8 \/ Z- X$ V
Experience with DFT and timing tools is preferred. ! c  k# X- [4 n' L
Experience with ARM platform is preferred.
' S# x9 o4 F: [$ FExperience with low power design flow is preferred.
7 P! q3 p- X" ^3 |$ BExperience with system verilog is preferred.
5 X0 b" Z& ?% a8 t9 [Good organization and documentation abilities  ( L2 j* d( S+ F" S6 D
MS in Electrical Engineering and Computer Science with 4 years of experience in SoC design
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11#
發表於 2014-8-15 13:50:55 | 顯示全部樓層
芯片设计工程师# u9 y9 W# W: W( `1 J4 Y/ C
6 u6 D& [6 ~" Q$ z3 i0 h$ f& t
公      司:A chip design company" ^, p* s3 @, P9 c; r$ S) U/ D
工作地点:深圳
$ h9 V/ s( S1 K4 W: e* L/ K, o4 l) I- z
岗位职责:
( N' A- Z+ t5 f7 w2 ]     1.芯片模块的设计与验证;  4 a! Z# W( q( L' W, E
     2.独立完成模块级结构设计,RTL实现以及相关验证工作;  : @2 Z/ _$ o) [+ D/ w' i; X
     3.参与FPGA系统调试和验证;  # }8 d' X! y2 ?+ u$ N
     4.参与芯片设计整个流程。+ |. j% M8 z; s
1 }9 ^& Q. z% _' M
岗位要求: 1 l) K6 ~: w/ Q6 H
      1.大学及以上教育水平,电子类专业
- n/ C( V+ K: g. h% s0 h% L# |9 Y) d      2.熟悉数字集成电路前端设计与流程 ; R, T! R) K3 k, e
      3.有数字集成电路设计与验证经验 , \9 s( s) G3 V: ?
      4.团队合作精神
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12#
發表於 2014-9-16 14:06:22 | 顯示全部樓層
FPGA工程师
; N8 |7 W, y; J' n/ `公      司:A famous IC company+ [# y3 B% T5 D+ S" ?$ m, I# p+ ]: `
工作地点:上海
& q' t4 Q. B7 y  V# O! Q. k% z/ V( {
岗位职责:  - c" P5 F8 \8 m) X+ o  K
1、负责各种FPGA原型平台的搭建、调试与维护  0 j- q% P) \$ g
2、根据项目需求,承担各种IP和SOC芯片的FPGA验证  
2 [, F, }3 @4 A3、设计芯片项目的原型平台,协助软件工程师完成底层驱动编写、系统移植等  
$ }  F8 p5 S" P8 c
* s' A1 Z, E' I职位要求:  : C4 Y3 ?  a# t) c2 L  b+ Q7 x
1.大学本科及以上学历,电子、通信、计算机或微电子专业;  
! x/ v; `$ R4 G7 ~2.有扎实的数字电路基础,熟悉Verilog等硬件描述语言的编程;  % _5 A: Y" r' G  l% n; ~4 x, i
3.有一定的嵌入式软件开发和板级硬件电路设计基础;  . {' V) V8 d" u
4.1~2年的FPGA相关工作经验;  " f- O3 N4 c* j* @- l) n* J4 X
5.具有较强的学习能力、沟通能力和良好的团队合作精神;  
. ?1 h& k$ o0 [( q2 J7 m6.有大型SOC芯片的FPGA平台开发者优先考虑。
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