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Analog / Mixed Signal Examples% [$ }, D! Z0 W5 H
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Behavioral Models of ADCs
( j9 D/ S5 p1 _* Y6 ~( A\ams\sampling\; sampling_101;
. N4 J8 k+ ]# W! t! i! N( w1 q Sigma-Delta ADC 1st order modulator $ cd \ams\adc\; dspsdadc2; $ z- s) A2 Z! b+ H
Sigma-Delta ADC 2nd order modulator $ cd \ams\adc\; dspsdadc3;
1 q0 P+ }3 ]3 Z9 o* b Sigma-Delta ADC 2nd order modulator discrete time (switched capacitor prototype) $ cd \ams\adc\; dspsdadc4;
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Behavioral RF/ A1 p6 ?# O1 a" g; J* Q3 B, x: \
Measurement of Lowpass Filter Freq Response $ cd feed_fwd_2;
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PLLs ( P9 @; r2 J" I* k
VCO with phase noise $ cd " ^0 N' C/ W9 \$ Z8 ]5 @
Pll with freq domain instruments $ cd \ams\pll;
3 {. b M+ I* u( m Pll fractional with analog compensation $ cd \ams\pll;
, j; H, P) i: G4 H3 s* H5 {4 A2 ] T Pll fractional with digital compensation $ cd \ams\pll;
8 k C$ u- r" T+ w- C) g4 _ Pll optimization (Nonlinear Control Design) $ cd \ams\pll; 6 P6 x1 \& s1 K* \4 ^7 }1 Y3 K
Carrier and Symbol Timing Recovery (NCO->ADC) $ cd \ams\pll; carrier_timing;
) X; n: X1 B, M+ {3 \6 n Carrier and Symbol Timing Recovery (Fractional Delay) $ cd \ams\pll; timing_recovery_1; |
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