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Senior Digital Design Engineer* K; B) d4 F5 b+ @6 x
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公 司:A leading semiconductor company( E! W3 `' n% i0 g/ m! {9 F& |0 h
工作地点:香港5 k. n) `, {5 l' K
" a" ]" T2 h+ K" UJob Responsibilities: - l' M( z% I; M
Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis ) g4 f1 F1 N9 Y5 F" ~0 m) t
Develop verification environment and coverage closure 6 f" K3 ]3 p, I3 I
Support wafer level testing and silicon evaluation
2 M3 S: @* `4 C; m4 h& K1 O Prepare technical documents |8 _# Y# N- @( E4 T
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Job Requirements: 4 c+ Q+ X- A9 {& S
B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage3 l1 J3 }$ c) |2 J1 B
5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations 9 F7 |, q0 }- T& A7 T2 I
Knowledge of SoC and embedded system. ( f3 Q) y, a+ j K
Knowledge of scripting languages such as Perl, TCL and Make 0 l! s7 M$ e& v E
Candidate with less experience will be considered as Digital Design Engineer |
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