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Senior/Staff Design Verification Engineer
$ z j. j$ _+ ~公 司:A famous IC company* ?3 W2 J4 _- ]3 f# Z9 z, ~7 o
工作地点:上海7 ^5 x1 C5 b9 ]2 a6 P. H
( r4 T, g. z9 p# O8 b! b, c+ BExternal Description: 7 ^/ }. r1 o S& r
- work closely with designers on verification test plan definition and test development " B+ }/ [6 @5 P/ F, H7 h8 l
- work closely with architects on performance modeling and validation 6 [% b) T+ O, o( b2 `1 ~
- regression infra development 7 I# G# L- n0 R# r
- coverage analysis and enhancement
8 T; `4 C7 A; {3 q3 \8 ^, ], z) R- behavioral model and BFM development
0 @/ V% q6 s% c- unit-T and timing gate-level verification , N- @4 s9 A! K4 r/ N
- develop IPs verification suites
& x5 m1 t- U+ r; I/ o; {- R. R- silicon bring up and debug support
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+ ^; d! j" k5 Q/ ~# D' }) l8 RQualifications:
6 ?, g6 n3 ?3 S. Z1 `- Z2 vMust have: 0 c( D8 _; v, h& Y2 v" j
- minimum 4+/8+ years of ASIC verification experience
5 C* \, x: ]- d$ u. r- BSEE degree or above
) r, Q& c" s% n3 G- strong programming skills, proficiency in C++, system verilog
: L( }% X/ G/ C. N2 W- working knowledge of scripting language (Perl, Python, etc.)
8 n9 H" f5 e6 S) Z7 [/ j- working knowledge of verification methodlogies such as VMM, OVM or UVM 3 ?, f! _( Q& g2 [3 H) {
- good communication skill 8 V! m# w* k! g0 X; z6 ]
- good team work spirit " \# m0 u& K8 z7 _5 J
2 w" j% i6 Y H/ B' j6 u5 P$ q7 nNice to have:
- v) J. B ^- R- q) C9 k* \- familiar with DTV/STB architecture, design, IP and system |
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