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//可直接透過synthesis tool用於PLD,FPGA不可 LUT delay則要採其他方式。% k+ o& K! f7 W# i7 w {
//所有註解都要保留
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`timescale 1 ns / 1 ns
. b2 X* |2 p$ @3 O" ]module xclk(sclk,ena,set,outp);
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& y4 n; ~1 ~; \: r, Jinput sclk,ena;8 t1 a, \( @# e; k
input [1:0]set;
, D# _" I% v( Moutput outp;
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wire outp; }/ ^3 i, I, T1 |$ B3 e$ J
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" ?# ~- G* r) a- g/ x/ @" r9 t/**** Node preservation for nodeA **************/+ \* n, y J+ E+ H
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//exemplar attribute nodeA_5 preserve_signal true( I4 I' |8 u- a5 L3 U- ~2 R
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//exemplar attribute nodeA_4 opt keep
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/**** The following comment form also works ****/
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$ j! ?& J8 a5 A6 t0 t* ^//exemplar attribute nodeA_3 preserve_signal true
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//exemplar attribute nodeA_3 opt keep
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; n9 b m/ y/ Z/**** The following comment form also works ****/
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//exemplar attribute nodeA_2 preserve_signal true
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//exemplar attribute nodeA_2 opt keep4 G4 @4 s2 w+ `1 _1 b3 {
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/**** The following comment form also works ****/: N3 U4 }% X5 o) n3 C% v
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//exemplar attribute nodeA_1 preserve_signal true
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//exemplar attribute nodeA_1 opt keep0 S# C1 x1 d+ M& o) Q
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/ z$ \9 I: u( V5 b2 h4 W/**** The following comment form also works ****/
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+ @1 t$ N6 e( C8 O8 ?% w* b4 k/ |$ L/*exemplar attribute nodeA_0 preserve_signal true
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! N \, a2 p5 jexemplar attribute nodeA_0 opt keep*/ 3 V4 Z% q) ?$ m) v4 N
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7 h X$ ^! _3 ^0 swire nodeA/* synthesis syn_keep=1 opt="keep"*/;6 h% x( D. Y3 r) m( y: [3 o
wire nodeA_0/* synthesis syn_keep=1 opt="keep"*/;8 |" O3 D0 B+ @$ c: i; [" I+ A% b
wire nodeA_1/* synthesis syn_keep=1 opt="keep"*/;
- d. ~! U, {( |- Mwire nodeA_2/* synthesis syn_keep=1 opt="keep"*/;
* f+ H N1 ~* T5 ?wire nodeA_3/* synthesis syn_keep=1 opt="keep"*/;
% `5 y8 t: i6 Vwire nodeA_4/* synthesis syn_keep=1 opt="keep"*/;( b9 S0 c, A! E8 b7 b9 h$ I
( E- U8 n9 y. {. F1 ?& o2 Oassign#1 nodeA_0 = sclk & ena;8 S2 ]; D3 E6 y& J( Z" {
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assign#1 nodeA_1 = ~ nodeA_0;( x0 ]6 Y% I- y" t
assign#1 nodeA_2 = ~ nodeA_1;
* n$ v9 u5 O; g- _% oassign#1 nodeA_3 = ~ nodeA_2;1 M1 A' E2 g, W3 @# ]) \( E2 [ U
assign#1 nodeA_4 = ~ nodeA_3;
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reg xout;5 ?/ i# K& n( Q! E( Y$ z' X
' L: h: F6 v: n" Y8 Z! Ialways@(nodeA_1,nodeA_2,nodeA_3,nodeA_4,set)# a9 j5 b' M& p3 I
casez(set)
$ D; A6 j, g, a2 b 1: xout =#1 nodeA_2;- b" r# o1 A- ^) ^" H
2: xout =#1 nodeA_3;4 V% @- J! a0 Y+ P/ p1 Y* }
3: xout =#1 nodeA_4;
; P7 Y2 \* v! b5 c; V' v2 v default: xout =#1 nodeA_1;
0 M: p n) ~ J; y/ m$ z endcase C5 c: K& l) ]0 H5 r3 |- ?
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assign#1 nodeA = xout;: {; L7 w( `5 `0 `
assign#1 outp = ena ? nodeA^sclk : 1'bz;
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endmodule) t5 L1 o* y1 w) V
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% E4 e1 k9 _2 U3 v, C# _+ h`timescale 1 ns / 1 ns
# x% b& p+ A/ \module xclk_tf();
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/ P% k3 b1 b) S( p// Inputs
" E. f, @6 N4 B- F0 ? reg sclk;
' P8 q$ [+ x% b+ F3 w7 U8 q reg ena;
5 _* P( Q4 A4 d+ m/ p. W; e" J reg [1:0] set;
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. y! K/ O, c" t// Outputs
7 |/ }0 y9 n* _. Z5 q wire outp; R E4 O* z' {2 S# F; v3 W
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y% f& t8 o o xclk UUT (
* J: B, H1 m0 v; E" p/ } .sclk(sclk),
6 ]/ |" v, [& v- s .ena(ena), # s- _/ W% n. f
.set(set), 1 `' }+ j" E0 F3 y( V
.outp(outp)
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& {) H% H" `7 \" _ initial begin
' y9 g& x! w, Y sclk = 0;
2 x& @" j' T; f: O ena = 0;
4 \5 H/ a+ A& [7 N) f/ k0 H set = 0;
! ]9 G' i% k# Y% } end
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always# 5 sclk = !sclk;
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initial begin
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, z+ K; H* x7 s; B ena = 1;
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set = 2;# U3 b [; z' C, q6 n8 j5 l
#2000
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$finish;% C3 k% M3 ^6 t n7 Z% t
end
( j# v! L6 h( \1 @# Yendmodule // xclk_tf |
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