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我目前在設計一個pipeline的電路,且有防bubble機制,但在設計的過程中有些問題~6 h6 P) @; h8 n6 s0 y
想請問一下大家!!
1 j& \& e5 b0 ]4 ]; `& q該怎麼設計?$ r# Q! @4 b: F" b6 M4 d! P8 r
以下是我需要的功能~
: c6 F5 @% ^2 w | | | | | | | | | | | | | | | | | | | The next stage data full signal | | | | | | | | | DUT full signal to preceding stage | 0 X P& z1 p0 x0 z5 d
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6 O8 \7 Q2 I. f- TThereare 5 pipe stages in our pipelining design. 2 N; y7 ~+ e- \4 n
It means that the input data can beobserved at the output port after 5 clock cycles. & f7 C( E0 e- t. d6 W) c2 o( n
All the stages must be readyto proceed at the same time.
# v! W0 r+ f2 ?- O( PWhen d_full is active, you have to keep the outputdata until d_full is disabled. . A f: {3 C) }/ y; H
If d_full is active and all the pipe stages arebusy, you have to generate pp_full to inform the preceding stages to hold data.
$ F |8 |) `3 F! DThe pipeline bubbles haveto be eliminated when d_full is active." C7 ]& d5 ~) A O# x# ^
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