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Staff Verification Engineer
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& ^' n% _+ ^0 p& ?& R公 司:one famous IC company
r4 U+ o, P$ D; h工作地点:上海
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Qualifications
" ^4 D6 z. e* S. f: t2 yMS in EE/CS/ME.
. _4 N' f/ u% a# D: yMinimum of five years experience. 8 b" ], p$ G/ t) ^
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
- ^1 J: ?* }5 n0 w% X$ VCandidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
" w. h9 B8 V8 @4 X$ B V% K# QCandidate should be familiar with industry standard ASIC design and verification tools and flow. 4 w' F9 U/ z+ Y( _; S
Good knowledge ddr protocol and computer system achitecture would be an added advantage. ! o: H& K8 w* A+ Z
Good knowledge of Perl and shell programming would be an added advantage.
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/ t7 e! C$ E& @7 [Responsibilities:
" ~; H& Y& y# |9 ^-Understanding the expected functionality of designs. & m/ W5 ]' D2 U* p5 P+ h& |
-Developing testing and regression plans. - N& m, v0 i& N4 {- ]
-Designing and developing verification environment.
6 J. {; Q f1 d5 b! G-Running RTL and gate-level simulations/regression.
6 `9 [; `8 e: E L" |$ S-Code/functional coverage development, analysis and closure.
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Requirements:
; V( _6 }$ ]& f6 f$ R" GExperience & Skill: 5 Years 3 R7 c# D* f& k& d- _- _1 V1 w" E" y& x
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
+ s! k: n; z. u& H! @ [" N-Knowledge in ASIC/FPGA design process and verification tools. % G3 W1 t6 n2 s' C/ Z/ a+ u
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
+ l& [* U/ }6 k, u5 |& C" }" D* J- Scripting and automation skills (tcl, perl, makefile etc) a plus. 6 r+ f5 B: C9 Y( b
-Familiar with C/C++.
' k9 L' g# g/ U. H/ R-Knowledge of DDR protocol a plus. * o- R: U0 a, ^$ I* y% ]
-Independent and self-managing. |
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