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This thesis discusses an alternative jitter removal circuit dubbed here as the Jitter
{& _0 c" U& t1 p$ ^% Q. Q9 R$ yAttenuation Circuit (JAC). The goal of this circuit is to provide jitter reduction performance
4 ^1 M! ^5 X' {/ Qon par with commercially available PLLs, while being relatively simple to design and use as+ c' J' r1 w% Z+ l3 B6 b2 { p
an on-chip solution. The main difference between the JAC and PLLs is that the JAC does& j3 a2 M/ a# m V
not guarantee any phase alignment with its input. Its sole purpose is to remove jitter. In: [, [! R" I. g' X
the following sections the effects of jitter, present methods to reduce jitter, and application) p. [7 e) }% f+ t' \; Y
of the JAC will be discussed.
0 C* B, E; L: [% ~; ]! K' a- z8 M t8 ]& A' @( ?
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