hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs
9 M, s5 u: q! E7 y; T
要怎麼定義用
plot LX??

8 M* E7 z, e( v7 B/ ?) z1 j請各位幫忙一下

小朱仔

直接下.op及.probe
' C! A# ^$ e1 U$ W) H) {& T+ F找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .

$ X, D3 B0 l- w0 hCgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.


For your reference.

0918429587

CAB_BS    LX28
2 n- t3 K8 e5 o) o0 |CAB_BD   LX29

4 T$ A- t) p6 c+ A% s7 [其他我找不到
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
! z# v4 w9 z* o( D( B6 d# W: s這是 CGDBO  CGSBO CBGBO

不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
# |6 W) _% S1 l2 z* x5 OAn example for your reference...
; b- _$ s- C! e3 |! n" `# W
----------------------------------------------------------------
# S. M/ P( K) |( r- c***** Gate Capacitance Plots *****
.lib 'your_component_model' lib_corner
.temp operational_temp
.option dccap=1 post
! m. n2 W* Z' t# S' z6 k0 v& O" Om1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
vd n_drain gnd 0
vg n_gate gnd 5
vb n_bulk gnd 0
% h6 P6 c! d5 v7 y' _; N.dc vd 0 5.0 0.1
.print   CGG=lx18(m1)
( o# m9 O: o/ W0 T+        CGD=par('-lx19(m1)')
+        CGS=par('-lx20(m1)')
+        CDG=par('-lx32(m1)')
' [8 J1 B0 U$ M8 F; z3 [$ S+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
4 V% G: L2 A5 ^* \- X# M8 J' Q* E.ends

----------------------------------------------------------------
" |% O( V) w2 P9 V# _8 WSix capacitance are reported in the operating point printout
* T! C+ x" @/ C2 H# J7 x    cd_total = dQD/dVD
    cg_total = dQG/dVG
    cs_total = dQS/dVS
    cb_total = dQB/dVB
    cgs = -dQG/dVS
4 p: Z. U: k) ~+ M* X& Y    cgd = -dQG/dVD
+ S0 j: m( n+ N" DThere capcitances include gate-drain, gate-source, and gate-bulk
overlap capacitance, and drain-bulk and source-bulk diode capacitance.

3 @7 ]/ k( K1 g2 O/ L$ zCGG = dQg/dVG
CGD = -dQg/dVD
CDG = -dQD/dVG

The MOS element template printouts for gate capacitance are LX18~LX23
, E: F7 C: h% S0 fand LX32~LX34.
( ^* C4 Q( ?- R7 v  d; ]
LX18(m) = dQG/dVGB = CGGBO
LX19(m) = dQG/dVDB = CGDBO
LX20(m) = dQG/dVSB = CGSBO

LX21(m) = dQB/dVGB = CGGBO
LX22(m) = dQB/dVDB = CGGBO
4 n' `, t) o( m. h% x/ eLX23(m) = dQB/dVSB = CGGBO

8 i& Q! U* G6 X2 W5 ALX32(m) = dQD/dVG = CDGBO
LX33(m) = dQD/dVD = CDDBO
LX34(m) = dQD/dVS = CDSBO

The equation shown above is for an NMOS with source-bulk grounded
configuration. Refer to the user's manual for more detail ^^