hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs

要怎麼定義用
+ S/ R* E2 }0 f4 ~$ s. Cplot LX??

請各位幫忙一下

小朱仔

直接下.op及.probe
找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .
1 Z5 N2 G# g9 S/ V
' X9 h2 @2 \, sCgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.

0 D! |9 r1 s4 V* W! a
For your reference.

0918429587

CAB_BS    LX28
* R9 e+ _. I8 w! a! i. UCAB_BD   LX29
( p) O! W- j5 P# Z2 }% X+ m( u( T9 j
9 Q1 K) N# t% A其他我找不到
  V! o( ?6 k0 z: k& OCgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
( m) Y9 b) q. Q/ K% i$ L這是 CGDBO  CGSBO CBGBO
5 u( {2 J( S" K+ z" M$ `; y
不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
( `- ]. }- f5 Y1 l5 q1 _& [An example for your reference...
1 T* C* a. U  d7 d: Q( |1 v% C
----------------------------------------------------------------
***** Gate Capacitance Plots *****
* |8 E! {  a9 @$ {: n" K.lib 'your_component_model' lib_corner
.temp operational_temp
$ |% ^- H2 T4 e  f.option dccap=1 post
+ T! S$ z$ A8 K& rm1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
vd n_drain gnd 0
vg n_gate gnd 5
vb n_bulk gnd 0
.dc vd 0 5.0 0.1
2 }0 Z3 l/ P( M8 u& x( w9 C.print   CGG=lx18(m1)
+        CGD=par('-lx19(m1)')
$ g. u- c; j3 \& p: @+        CGS=par('-lx20(m1)')
" [) @2 L# [5 d) `  U3 R; K0 E! U+        CDG=par('-lx32(m1)')
/ E) B1 x% M6 v+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
.ends

----------------------------------------------------------------
8 j3 r8 y& i0 B/ KSix capacitance are reported in the operating point printout
    cd_total = dQD/dVD
+ k, y" |9 q: j) z    cg_total = dQG/dVG
    cs_total = dQS/dVS
& l! Z$ ?- }$ l; B    cb_total = dQB/dVB
* D3 S# |4 G, j7 G! O    cgs = -dQG/dVS
, c$ q9 C9 K( w1 n5 S4 i    cgd = -dQG/dVD
There capcitances include gate-drain, gate-source, and gate-bulk
overlap capacitance, and drain-bulk and source-bulk diode capacitance.

CGG = dQg/dVG
9 L' E; ~0 k+ SCGD = -dQg/dVD
' a: U; u; {* G$ L+ K# ZCDG = -dQD/dVG

The MOS element template printouts for gate capacitance are LX18~LX23
and LX32~LX34.
" Y  J& @( D5 ~# c$ ?
LX18(m) = dQG/dVGB = CGGBO
LX19(m) = dQG/dVDB = CGDBO
LX20(m) = dQG/dVSB = CGSBO
+ L8 a. s/ z( d8 l5 o9 m
LX21(m) = dQB/dVGB = CGGBO
LX22(m) = dQB/dVDB = CGGBO
LX23(m) = dQB/dVSB = CGGBO

1 ?& h4 e& s" T. _2 i& H/ r! xLX32(m) = dQD/dVG = CDGBO
8 G! _1 J. m+ j% Q+ e. mLX33(m) = dQD/dVD = CDDBO
) e0 _2 f6 U( }, l7 \& aLX34(m) = dQD/dVS = CDSBO
' l' k* I& }5 o: L  H
3 [5 d' N' W' O5 c! q6 a& h) DThe equation shown above is for an NMOS with source-bulk grounded
2 N+ W$ s& B* p4 F; z% U% Xconfiguration. Refer to the user's manual for more detail ^^