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0. Check circuit topology and connectivity.
4 M) B8 q8 [) d& WThis item is the same as item 0 in the DC analysis.
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1. Set RELTOL=.01 in the .OPTIONS statement.' u6 o0 `" x! C1 L+ j3 w
Example: .OPTIONS RELTOL=.01
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2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.7 B$ ^+ x, ^9 G- y3 n; G
Example: . OPTION ABSTOL=1N VNTOL=1M4 W2 S2 o$ J$ ]
1 R! p; ] }4 S. g& Q# |6 o3 j! g: C/ W3. Set ITL4=500 in the .OPTIONS statement.
1 i1 R( x) }2 R6 _Example: .OPTIONS ITL4=500% G1 z9 a% ]( t) `8 C
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4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.: H8 L6 R. E& G) E, c
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5. Reduce the rise/fall times of the PULSE sources.
4 |& P. q' h" B" k% HExample: VCC 1 0 PULSE 0 1 0 0 02 _2 Q( \! k/ l% S2 c: w% v# k5 D
becomes VCC 1 0 PULSE 0 1 0 1U 1U
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6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.
! @: r# g W y: i- ^. x& B$ P. ~Example: .OPTIONS RAMPTIME=10NS8 x$ ^! ^3 X9 L6 h d) Z+ a
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7. Add UIC (Use Initial Conditions) to the .TRAN line." \6 N- {" {! ~+ c! u2 X4 R* q; p
Example: .TRAN .1N 100N UIC
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8. Change the integration method to Gear (See also Special Cases below).% @ \4 c' o$ i+ q8 q& j
Example: .OPTIONS METHOD=GEAR |
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