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Senior ASIC engineer
客户 a start up company with innovative technology# r5 ?5 B% O) E
地点 Shanghai. X6 o! I+ s) Y1 S+ K( X
: r5 I# t6 s4 H* ^3 Z职位要求% D/ Z1 |" f! \) A# E3 J! q
5 + years experience in ASIC design -> must
. S7 D% J1 W6 V9 [- Y; z· MS in Electrical Engineering (or equivalent) is a must have# X6 c( q; R- @ j6 l# s
· Experience with WIFI baseband/MAC or related wireless baseband technology desired -> plus
% ~, H, ^2 v Y' O2 S3 e( L· System on Chip (SOC) Integration Experience, including AHB/AXI, CPU integration -> plus* g n7 s/ o7 `, ^, m' v; K, G1 K
· Experience with interfaces such as SPI, SDIO, USB -> plus$ P" @3 p+ s- [9 I8 y5 t
· Working knowledge of networking protocols such as TCP/IP, 802.3, 802.11 -> plus+ X ]! u) y q! u& ^
· Must be expert in Verilog RTL language -> must
( r6 c+ i X U: R! \# P$ F· Must be familiar with the ASIC design flow from RTL through synthesis, including the tool flow. -> must ?1 {6 F _3 i2 B: |( y
· Verification experience – Verilog, System-Verilog, Coverage Analysis -> must for verification engineer, plus for design engineer. A+ Q: _% ` Z5 v& L1 G3 x, B
· FPGA emulation experience -> plus
7 }2 O9 R4 I" M% B1 e: l6 c$ D· Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging -> plus
8 o. M2 r5 d c3 M ?" j· Experience with digital backend |
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