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[經驗交流] 請教90/65奈米,SOC Tape-out一次NRE大約多少

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1#
發表於 2009-8-13 10:26:46 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
如題' V. n; c# l3 n
- y+ `$ @) F& P! p
請教業界各位先進: D" O) t+ r5 C0 g3 `
目前的chip開發,需要多少投資?# ~' z4 ~: x3 ?0 o8 ]
首先是假設 Febless design house.
& @" E( Y6 g. X; b$ a自家由algorithm 到 RTL simulation 完成/ S, Q( O* ]$ b, V$ R
後端包給 backend service 公司 (layout, mask, Fab, assembly..)9 J& o2 `+ D! M) h" k
以 ARM9 or ARM11, AMBA2.0 為platform6 D5 M7 ^# C, `1 ~1 l! e
那麼
  R3 b: E' y8 p# r: `0 Q/ ^; O# V  (1)90奈米, NRE大概多少?
4 u* f& }1 R" T  (2)65奈米, NRE大概多少?7 w* C  g, x0 N. |% _8 j$ V  r
  (3)或是您知道其他製程, NRE大約多少...
, c+ v. l4 U: v2 {' P! _6 [6 y) n* Z8 D1 }( P
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2#
發表於 2009-8-14 01:17:51 | 只看該作者
Which design service company you will go to?
3 s; y# x1 z6 c: }- [4 G( dHow many mask layers it will be?7 }' J9 r8 g/ C% }) a8 t- N# L
Besides, ARM, any other IP, like DLL / PLL / EDRAM / USB / LVDS..... and who will be the IP provider(s), wafer Fab? design service companies? or 3rd parties?) r9 f) T! W+ \
How many chips you need? A full set mask or MPW?
2 D' k& T$ a* u' rWhat package you need?
3#
 樓主| 發表於 2009-8-14 08:59:04 | 只看該作者
Well,
5 N4 M8 @4 d% f' [8 d* W7 n7 W' O) I; H; Q: A" r5 q( G
I just estimate the investiment of a ASIC team.
, X5 {/ O0 B/ Jnot servey for a project.- R  G* b6 J6 b9 q+ X, z9 D  q" m
So, I just want to know the range of NRE., s$ C! d' [# W) S( x# @- k- I

# i- u: ~7 l. H/ XFor example, It will be
+ c* A. `: H4 o% p% o, a( X9 h(1) 5,000,000 NT$ ?# _: I5 M7 Z, ^: j9 O; F
(2) 8,000,000 NT$ ?
8 J  H- Q- f- d(3)10,000,000 NT$ ?
. V! S$ j# d- U; z0 r; K7 b$ l: l(4)12,000,000 NT$ ?& d- \- ?! R2 {, R
(5)15,000,000 NT$ ?
3 I( ~, D( U8 n3 h% u7 E5 `+ j6 |2 W) N% y5 ?. d' C% g: e4 w4 Z
Sure, I understand following things:5 p4 D! q/ _* u% h7 y
- full set mask cost more
& V" R: m9 N: m - PLL/LVDS... analog IP are extra cost
" E! F. R3 V- N+ k# Q1 i - pin-count and area also influence cost" a) s+ Y" ^9 \
- different package also cost different
- [; N  Y3 l  h- Y( O" h) z) Q% z9 x( y9 G7 V1 m
Therefore, if really need information for estimate,
! k6 ^+ ~  c6 I  I. U* kjust for example.  _+ p( N3 b& _( P4 ^
Let's assume a SoC for FullHD TV application7 Y! ^8 ]+ l6 O9 m8 o3 u$ V. o
it will include, \& @3 r5 f% B* [
  - ARM AMBA
7 X# U. L; |, M5 P  - DDR2 I/F
9 g: o3 w* Q% m% g) P1 B4 [- H  - GPIO, IIC,...+ v" j- o& ?9 C  y* D- W9 \
  - LVDS out (dual link)
1 J  ^: s) F4 @% t, a& T  - Video-in: HDMI(1.2)x2, VGA, YCbCr, A/V, S-V, SCART,% \" w$ i% T$ D7 h% h
  - 12bit ADC, 10bot ADC x26 ]) }; R# h7 X
  - PLL/DLL
7 R9 x/ A- F6 I( D. V' @, }! m. X  - 256 pins 以上9 Q8 F! T! S- Q- F

4 u& v& V( k2 @: {* ?3 R0 j* TThan,... any idea about NRE fee?* m, {  K, g) z
again, I just want to know the range
4#
發表於 2009-8-14 09:25:01 | 只看該作者
if the ARM and AMBA is hardcore,
) @6 g8 y4 R0 P5 L* {1 @$ k. Lbasically 65nm-->USD$1M above and 90nm-->700K above! {, [/ U6 c  Y4 H+ [
and base on different foundry has difference price!+ I; |  f7 j! D( r& q
this price did not include any specific IP like TV encoder, decoder, vedio codec....
( s/ {9 S2 p7 ]& M1 Land did not include the ARM licensee...( U, H9 t9 m& b( i
actually! it is not so much IC design in Taiwan tape out 65nm till now!
5#
發表於 2009-8-14 09:28:45 | 只看該作者
sorry, this price also did not include the shuttle or pilot run wafer(basically in 65nm will be USD$3xxx at 13pcs wafer)* x/ z( I# d0 _; m, ?5 a' O
and package&testing, so you may count it at USD$1.3~1.5M if you are running turnkey solution!
6#
發表於 2009-10-22 11:06:45 | 只看該作者
need 1M dollar?
7#
發表於 2009-12-15 21:05:38 | 只看該作者

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