請問由Verilog code到IC layout 需要哪些軟體

leesg

問題, 已完成 Verilog code 設計, 模擬(ModelSim)
想要用軟體直接 run 到 IC Layout 產生 die photo,
要用什麼軟體組合 ? (輸入 verilog code, 自動跑出 IC Layout)
9 a' h+ U9 `2 g1.
( N! A5 J4 e& E4 P) Z3 W- _design compiler + Astro ?
1 J6 h3 ]! T0 c+ n
3 Y" U6 s; `* `3 X2 m/ W8 W2.
synopsys IC compiler ?
4 ?" l0 A8 _( Y& l+ \2 x/ Q
* |$ m) @9 M3 B  P5 ~3.
) U6 G( A# t+ o! p6 v0 I% }8 ncadnece virtuso ?

lee100

Synopsys R2G flow
1. rtl simulation by vcs
2. synthesis by design compiler ultra with dc/dct mode
" T2 \; h! i7 ^( |: W3. dft insertion by dft compiler
5 K; E% M& V( f' J. |' ^4. jtag insertion by bsd compiler
' a" E1 ~) w; N+ |8 F5. ICG insertion by power compiler
6. pre/post-layout STA by prime time
7. pre/post-layout power analysis by prime time px
  U  {/ ~( X/ k& }8. PnR by IC compiler
. E- Q! }. j: F% a% i9. post-layout SI analysis by prime time si
( E. u- D7 Z4 v, b( g5 J0 U; h10. post-layout simulation by vcs

putechen

sometimes ,star-RCXT is necessary.just for layout PEX.

yytseng

after above place and route task, you need virtuoso or laker to merge cell layouts and do some editing.
( O3 a. d; @8 {+ l: \" vclean up LVS/DRC/ERC/ESD violations with calibre or (hercules, assura) tools.

ejean

1. magma is another solution
2. Astro  from synopsys
1 H) |; A( h" M5 T3. FirstEncounter from Cadence
) C# B! B$ o1 T9 y7 Y. H2 C
All with basic DRC and LVS, you have to run Calibre, etc. to finish the final verification.

ilovepachaya

私心推薦APR使用IC Compiler  效果很好