A Layered Verification Approach Applied to an AMBA-Based System

phoenixfeng

It’s common knowledge that the verification
stage for a given system is
3 d/ N1 |5 u, Z+ Yaround 70% of the overall design
effort and schedule time. Reducing
overall time spent in test creation and
! O* V; W! |$ B1 K4 K) ^  m0 Ldesign verification is a high priority.
, T/ D2 _$ j, l4 j7 t1 G7 b) QSuccess in these two areas increases
  r+ e% B' }) l" h6 p7 \* Zproductivity and helps deliver products
to market faster. To achieve these verification
$ M2 ]  ?. V; xgoals, engineers are constantly
  C0 T' e$ H5 N' }# f: m" G* mlooking for new and innovative ways to
8 k, Z/ w4 \1 z2 @conquer the verification challenges that
face them.
+ ^& i9 G6 ?, Q8 j: f2 I) ~5 fThis article discusses a layered verification
approach as applied to an AMBAbased
# ?0 O1 ]/ y! r, _1 A* A/ v& L. `system component. The layered
3 w1 M& e  q$ r0 {: uapproach is used to create a standardized
& h: ?3 v2 ~9 R" Everification environment that can
adapt as the design challenges
3 Y0 ?. [# g0 P# v: O1 V' Zincrease. Typically, reuse is very high
9 e4 w% p  K" y# q0 q2 T8 I8 fwithin an AMBA-based system because
many new designs are based on earlier
% i; y8 Y2 {: ^" qversions of the standard system. The
# D% ~+ M" p) Y. S' H6 `example shows the layered approach
3 R! i! ^9 Q% H# M, e4 |being applied to verify an individual
  q( E  |$ p) C$ J1 Qblock as well as its integration into the
subsystem and final system representation.

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