|
我目前在設計一個pipeline的電路,且有防bubble機制,但在設計的過程中有些問題~
" k! `( A+ e/ d) M4 l想請問一下大家!!
. b( N/ C' Q z. o該怎麼設計?
$ H& N7 K. b# O7 s, g ~以下是我需要的功能~/ r' w6 j; P6 s& g- N% w
| | | | | | | | | | | | | | | | | | | The next stage data full signal | | | | | | | | | DUT full signal to preceding stage | ; ~3 H2 b3 Q5 a; X
; D. ~2 u1 p& i+ w4 r5 }! U7 ^5 n8 b( j5 [: q. S! ]
Thereare 5 pipe stages in our pipelining design. * P' Q2 _, q( b" ^1 c
It means that the input data can beobserved at the output port after 5 clock cycles.
1 j' N% g/ l4 qAll the stages must be readyto proceed at the same time. & M3 w+ L1 A& @6 Y. e" l; ?
When d_full is active, you have to keep the outputdata until d_full is disabled.
+ S/ y+ W& J/ r! w0 J8 ^If d_full is active and all the pipe stages arebusy, you have to generate pp_full to inform the preceding stages to hold data.
. _1 p# P' @% `4 [The pipeline bubbles haveto be eliminated when d_full is active.8 X& ?' u# k! k* H4 ~
8 t! R4 J: y9 \ x9 Z1 Q- m+ R& t! k+ Z) C
$ v; h" K9 ]1 T- I
3 l2 j) e1 J2 l H
" Y: P' h5 j0 q( T; O0 B
3 W- \/ \( `. n Z5 Y2 E8 E7 ?8 o8 s F& Y$ K6 F% v
$ ]3 v7 U4 ]4 F$ h! { [3 J3 @+ h! n* z- S3 ~4 p. w; Q+ f
* W: U% Q; V2 a- {' ^0 J( Q# T
5 v% o9 j( k& b( _% s3 ?- |6 L
- K# ^" g9 ]5 P
1 ~6 L" E5 A4 H5 ]8 Z& H
( F! b" |) Y) q X' l+ d7 d1 Y+ R+ r$ `4 x7 G
8 U8 G& i1 P8 v9 G) V' k& Y, [' I$ Z0 j2 W7 O3 ?( R
* N$ o/ l; G' R$ ^9 ^ |
|