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//可直接透過synthesis tool用於PLD,FPGA不可 LUT delay則要採其他方式。
3 R% U5 ?# ^6 W% j5 F& u//所有註解都要保留- c3 G' j7 E9 M3 L. s1 l8 x
$ }: Z3 A) h3 x5 L`timescale 1 ns / 1 ns
( O* @. S' D2 E* Zmodule xclk(sclk,ena,set,outp);3 M" p6 w; ~4 a' }/ Z0 w
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input sclk,ena;
/ e7 f- |/ S s- j, k/ Tinput [1:0]set;5 Z- q" K0 [4 N3 `
output outp;
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# V5 N4 V% @/ }$ ]wire outp;
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/**** Node preservation for nodeA **************/) ^" x. f0 J+ ^$ q/ z$ e3 m
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//exemplar attribute nodeA_5 preserve_signal true
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" R1 v# m: ^* S( D+ R//exemplar attribute nodeA_4 opt keep: m) s! d1 A m5 ?" h1 |
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//exemplar attribute nodeA_3 preserve_signal true" g& q. L) k, G a
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//exemplar attribute nodeA_3 opt keep
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/**** The following comment form also works ****/" _+ J3 n: i8 l2 z k2 j" m3 w$ n9 q
?$ j, S+ I- k1 L, O. [//exemplar attribute nodeA_2 preserve_signal true, z% } D0 b* i5 L4 |
; p! A, ^7 m, `, K# h//exemplar attribute nodeA_2 opt keep" V( j3 ]: a5 I. n5 J @
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/**** The following comment form also works ****/+ P( q/ L3 w! y2 o& a1 E. B6 H/ L
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//exemplar attribute nodeA_1 preserve_signal true
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//exemplar attribute nodeA_1 opt keep8 N7 ~4 x+ P3 g' Z( o/ G* p
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/**** The following comment form also works ****/
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" C2 n8 x1 v* N6 J( v) ~0 M1 t0 r) ~/*exemplar attribute nodeA_0 preserve_signal true
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& |5 k" \# d8 h- o/ M% d; b- zexemplar attribute nodeA_0 opt keep*/
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wire nodeA/* synthesis syn_keep=1 opt="keep"*/;; a! R) n' \" u! s7 n4 x1 I5 R
wire nodeA_0/* synthesis syn_keep=1 opt="keep"*/;% D1 g$ J/ v- ? ]. n; @+ g
wire nodeA_1/* synthesis syn_keep=1 opt="keep"*/;% s7 j' c2 ^3 U5 ?
wire nodeA_2/* synthesis syn_keep=1 opt="keep"*/;0 T' W6 _+ i6 R# P5 N+ e! M" T
wire nodeA_3/* synthesis syn_keep=1 opt="keep"*/;
7 t( x$ K( R( vwire nodeA_4/* synthesis syn_keep=1 opt="keep"*/;
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+ q" y& k& ~) rassign#1 nodeA_0 = sclk & ena;3 w5 M! W8 I& q( i: ]4 q* e
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assign#1 nodeA_1 = ~ nodeA_0;
- j( a( n8 z) J" \& Xassign#1 nodeA_2 = ~ nodeA_1;, S+ L1 P1 E' n5 z- z
assign#1 nodeA_3 = ~ nodeA_2;7 U0 i2 \# } m$ s& ?2 p$ j+ U
assign#1 nodeA_4 = ~ nodeA_3; S9 n3 q0 ~% Z0 D/ w( _# c2 k; q# ^! J
! u4 S3 N% B1 i/ L# i2 mreg xout;
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, A/ h2 A* M$ t' ^: S8 Nalways@(nodeA_1,nodeA_2,nodeA_3,nodeA_4,set)
/ [, v& ]3 O' x0 K* `! A casez(set)
% O0 X. u( |8 B 1: xout =#1 nodeA_2;' T5 m( v, @5 F; [
2: xout =#1 nodeA_3;
* X- Q3 y) e4 L) k' h' o 3: xout =#1 nodeA_4;$ i4 t. {" d' u2 f3 Q) Z/ r- E
default: xout =#1 nodeA_1;
/ i4 O/ A4 M6 h" p% ?; V- Y endcase' l( h o; p" q
+ S! n. o6 A1 T# a- a9 \ sassign#1 nodeA = xout;
1 I6 \/ e# `3 H, V& K. Z/ n1 N& Bassign#1 outp = ena ? nodeA^sclk : 1'bz;
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endmodule
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+ ? a. ~& s$ l+ L- I N( m`timescale 1 ns / 1 ns
$ y0 [+ p& `3 u/ ?8 e' C, emodule xclk_tf();9 L( Q5 d" ?) Q( |2 p% `3 Y
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// Inputs+ {) e8 x {6 r' W$ R5 o
reg sclk;* R$ N5 ]9 B1 q2 w6 r! c* ~$ G
reg ena;
4 @- _( K% m& v; @% q& m' e9 S reg [1:0] set;
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. r- t8 k7 b k8 z) v9 ~. O+ O// Outputs( J. ~2 y' z7 Z8 T) k7 `6 S
wire outp;
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xclk UUT (
1 }1 C( E$ t1 i/ v m .sclk(sclk), + m. w0 Q7 J/ T! Z
.ena(ena), 8 X1 i/ ]' |3 w8 i; } d
.set(set), ! _" `4 A: [/ \) s* Q& M' j
.outp(outp)
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: V* U6 F8 O" ~; m/ |& X initial begin( O: K- i# t2 ~; U
sclk = 0;
! u( p5 ?* j/ ~4 C5 v' \. j, ^ ena = 0;
# W: n( T% B0 A1 c+ w% h set = 0;
* g7 K, q, A5 o end
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( s+ U5 l* y% walways# 5 sclk = !sclk;4 q0 @3 r5 P" T; k; S, S
1 h. M- D5 X C- m1 y$ ?initial begin
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ena = 1;7 O" D3 s* n# M3 t& @3 {& u4 h
#2000
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$ A1 ]- F( f# _3 }' W- V set = 3;
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$finish;# W# ?- O5 n( _- w6 I: w
end/ U0 G0 u) V/ k4 {: W& v
endmodule // xclk_tf |
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