library compiler建DFF cell的疑問

霜淇淋

各位好，小弟打算跑HSPICE改變一下cell library的資料
" p' v, K7 g% Y  l! \但有部分還是不太理解，以下是D-Flip Flop(DFF)接腳D及CLK部分
; [2 {1 @, U. G

  pin(D) {
    nextstate_type : data;
: A# s1 {( y# I6 e6 k* D# f    direction : input ;
    capacitance : 0.001165;
$ r5 E5 b( ?  Z. M* k- f/ X    internal_power() {
      when : "!CK";
      power(POWER_7x1) {
6 s& @9 y* J! c8 ?; O3 v- @        index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
$ N4 {& I6 Q& c' r) W# r        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
      }
    }

# }( g, g% S2 h- @" i3 K2 d' Xvalues值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?
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    internal_power() {
: b' M' \: f; x/ c- r% @) O  |0 V      when : "CK";
* e8 \& Q1 z8 [% b" c& K% w. m      power(POWER_7x1) {
9 @$ M. x% k. n# ^! Q3 h7 h        index_1("0.009645,0.016106,0.025991,0.046674,0.088957,0.216628,0.447814");
: Q2 C9 D6 M; n        values("0.000127,0.000122,0.000120,0.000119,0.000117,0.000116,0.000114");
' ?/ ~3 U& x' u9 V) H) Z" s( O      }
2 S: w* _3 q* C$ i    }
    timing() {
      related_pin : "CK";
      sdf_edges   : both_edges;
      timing_type : setup_rising;
2 G! {/ l" t5 U6 _2 i5 E9 ?* l2 v      rise_constraint(CONST_3x3) {
7 w5 Y: h7 l5 w' P% q3 ?        index_1("0.006000,0.217000,0.434000");
: J- ?0 g0 x( y3 O7 K! ]7 Z        index_2("0.006000,0.108000,0.217000");
        values("0.029659,0.026470,0.036963",\
4 m+ I: L4 B1 W9 `               "0.032032,0.023912,0.031939",\
               "0.004917,0.000010,0.004825");
: w" W" s" B' q2 s& }7 |9 m      }
, |  k3 H& f! _' O( i! V/ M/ k
values是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?
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' X' m8 b" f7 x; U) q      fall_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
1 \5 M, W: @9 [7 b, A3 l        index_2("0.006000,0.108000,0.217000");
        values("0.074043,0.058526,0.059156",\
               "0.152860,0.139810,0.137970",\
% j. _- j. f$ E3 S. s& }               "0.231770,0.216260,0.216890");
      }
    }

yytseng

internal_power() {
      power(POWER_7x1) {
+ [' D) g3 H. R9 ~. c        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
" H0 H; s: ]% c6 R3 kvalues值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎?
; G7 m7 V5 C: Q+ ^7 ^===> Wrong !
===> they mean while different input slew (transition) of CK, results different internal power
3 r# V4 J5 r- f8 H  K! M& C) o* h
$ }6 r: s. c6 p" a$ B/ W& y) Qmin_pulse_width_high : 0.061268;
/ u  S3 C, l# bmin_pulse_width_low  : 0.125320;
CLK Hi/Low的長度?
====> No, these mean minimum possible of clock waveform to prevent functional fail, for high (1) and low (0)

: O( `& D, y" x/ |! _      index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
% A! {4 `* I. y0 Z; q( b; C) b        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
8 \5 S, b) ?* _1 \2 D% }      }
    }
$ e1 p! w8 m! A2 J  h+ _+ E
values值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?
) n$ Y& R' e) l. @+ J7 y==> No, index1 is often input transition. here represents input slew of D pin
% I0 k5 N6 K+ G1 ?. w
# ~; i+ j. P2 C        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("0.029659,0.026470,0.036963",\
) V* o* N9 L1 @7 h) E5 B               "0.032032,0.023912,0.031939",\
5 b: P- U; a+ \' W               "0.004917,0.000010,0.004825");
      }
6 a: O) y% ?9 t
; b; Y$ G+ q9 E. zvalues是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?

# m: _8 ]. o0 t4 `  h/ v5 v: d===> yes, but you have to refer index_2 definition in the front of liberty file to make sure.

霜淇淋

timing() {
      related_pin : "CK";
: Q6 C; T9 y  k$ U- G      sdf_edges   : both_edges;
9 O' I( M% A% M. v$ t/ u# R; @, Z0 ~      timing_type : hold_rising;
) x& a0 \7 M* T: `4 b1 \2 k4 L/ v      rise_constraint(CONST_3x3) {
% @4 A9 m2 Y! L, }        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
/ \8 t$ c' i, H! u; |- F2 V        values("-0.005932,-0.005209,-0.015703",\
6 x5 {7 P9 I6 X3 D. Z$ |               "0.013887,0.014610,0.004117",\
3 v4 a3 _( S+ _/ Z6 N               "0.060728,0.056519,0.043560");
      }
+ o9 x$ n4 c" T* r# A      fall_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
) P! X! X) \, D- e+ n% A        index_2("0.006000,0.108000,0.217000");
2 a3 ]8 L) ~8 V# h; \1 }        values("-0.018261,-0.002744,-0.005839",\
, G' |/ w. v* m$ \: o               "-0.028829,-0.021521,-0.028745",\
               "-0.004426,0.053203,-0.004342");
* _: a9 D) k% V6 d/ {      }
, s$ A/ K4 \/ p: m' u* \    }
, q& u1 n% W8 f7 V+ l2 c  J  }
  pin(CK) {
2 c! y* ?4 y  |' p    direction : input ;
    capacitance : 0.001915;
, ]" _) a) e; P" K6 G    max_transition : 0.217000;
    clock : true;
/ a3 h' X5 J, P. \( l9 u" [3 C* q    internal_power() {
' F* O1 n% [' [2 [! F      power(POWER_7x1) {
, I7 I0 \" A7 e3 S# s        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
7 h7 s6 U8 [+ e7 f. l" c3 p& u+ ~! \        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
0 I6 R% M$ D& I& o8 ?) z' M* x      }
    }
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+ b1 [0 y  S7 ~+ D* t! \- |
values值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎?
6 x% H3 T. [- _
- h+ J0 o! A5 X' I# X* D; z    min_pulse_width_high : 0.061268;
- z! c! |/ S# @9 D/ G: x/ V    min_pulse_width_low  : 0.125320;

9 y; o8 L* Y, D7 m( cCLK Hi/Low的長度?
$ T4 P8 _5 s7 J# v3 J  }
, i( ?: Q! _/ h# v}
- {  s: V$ T' S+ r
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6 R& @! D4 H( Y0 B8 N  H5 V
3 j2 V5 l: l, E9 _有觀念誤解的話希望幫忙修正..謝謝

" I% Z" V$ ~" ]# l* A, H7 c& j[ 本帖最後由 霜淇淋 於 2009-9-17 02:03 AM 編輯 ]