library compiler建DFF cell的疑問

霜淇淋

各位好，小弟打算跑HSPICE改變一下cell library的資料
' a7 U& W) c  S! o3 b但有部分還是不太理解，以下是D-Flip Flop(DFF)接腳D及CLK部分

/ b2 ^. n( x% D, k# d
  pin(D) {
+ Y0 y3 X  b/ M2 L4 ]8 ]( L9 d    nextstate_type : data;
& x9 F1 a) ?! D; X8 K, B    direction : input ;
# a6 [) s2 _' ~4 Q# ~    capacitance : 0.001165;
    internal_power() {
: _: m6 F8 W( }% p" z+ |      when : "!CK";
      power(POWER_7x1) {
        index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
+ |1 A2 e* M" O  H  t      }
, ~* b% g  V& e- d7 c' ]+ c0 F) E    }

values值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?

! {4 t- \4 \9 t" Y5 X7 F    internal_power() {
$ }; i3 a# C0 l( o      when : "CK";
      power(POWER_7x1) {
        index_1("0.009645,0.016106,0.025991,0.046674,0.088957,0.216628,0.447814");
+ j6 O0 x( x  v$ j6 A/ g        values("0.000127,0.000122,0.000120,0.000119,0.000117,0.000116,0.000114");
! v  d7 b% o- O# S/ `6 O      }
    }
    timing() {
      related_pin : "CK";
4 u% b% F6 q6 }) B+ ~6 @0 \      sdf_edges   : both_edges;
      timing_type : setup_rising;
      rise_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
* }  {4 H) W7 @# C& ?        values("0.029659,0.026470,0.036963",\
7 r. I. e1 p& E& @- N; Q+ _               "0.032032,0.023912,0.031939",\
               "0.004917,0.000010,0.004825");
      }
; \/ Q. |7 O' K$ w" j
values是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?
. E$ u! n& e- g. i! _7 T
' a" ?/ J0 ]% K, h* R; m
      fall_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("0.074043,0.058526,0.059156",\
( r  J2 O3 I  E! k& D! ?               "0.152860,0.139810,0.137970",\
# |* P6 {0 S7 L8 {               "0.231770,0.216260,0.216890");
      }
    }

yytseng

internal_power() {
      power(POWER_7x1) {
- V; y  o, @. Q* L' z7 K        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
! L6 y4 l2 D7 V  k        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
values值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎?
===> Wrong !
9 [# I. Q+ r! u5 g) s$ Q6 W===> they mean while different input slew (transition) of CK, results different internal power

/ ?. `4 o2 x2 i8 ^. B, ]9 gmin_pulse_width_high : 0.061268;
, R* e5 W" x" |# U& K6 nmin_pulse_width_low  : 0.125320;
" P- t5 P1 x- [CLK Hi/Low的長度?
====> No, these mean minimum possible of clock waveform to prevent functional fail, for high (1) and low (0)
& [/ v0 H9 H5 P& c
      index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
      }
    }
. e, e. |( F. Z# H+ {, h0 p/ \4 ?6 |
values值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?
/ e7 M) |+ J! {8 i==> No, index1 is often input transition. here represents input slew of D pin

        index_1("0.006000,0.217000,0.434000");
: s( r8 p- @- S        index_2("0.006000,0.108000,0.217000");
) i# O8 f6 W+ {6 T        values("0.029659,0.026470,0.036963",\
; `  p1 r& ]. i) G               "0.032032,0.023912,0.031939",\
               "0.004917,0.000010,0.004825");
. `- l8 X! j7 A( h, h* M& t      }

values是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?

  U! i7 b$ e# Q1 q===> yes, but you have to refer index_2 definition in the front of liberty file to make sure.

霜淇淋

timing() {
1 I& U, w8 V8 W- {7 c% J, m4 w7 c      related_pin : "CK";
      sdf_edges   : both_edges;
      timing_type : hold_rising;
      rise_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("-0.005932,-0.005209,-0.015703",\
5 j' Y5 k! L  {2 i* x1 y, j               "0.013887,0.014610,0.004117",\
               "0.060728,0.056519,0.043560");
  @" Z5 b6 r8 j( Y/ i      }
1 p1 S& ?" M2 t  r      fall_constraint(CONST_3x3) {
2 O" p( P7 G5 Q. L+ k/ Z" n7 l        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
1 u) V! d5 w" I        values("-0.018261,-0.002744,-0.005839",\
" N3 l) a1 O8 A/ O& W6 Z$ t9 i7 ]& |               "-0.028829,-0.021521,-0.028745",\
+ E0 x. ]9 [. v  ^4 A$ T& d               "-0.004426,0.053203,-0.004342");
      }
+ h/ B: {6 L% S. V9 Y: ^+ @    }
! `% L7 A( y6 G7 }  }
$ [+ |1 p5 x' h. v; _, c2 P  pin(CK) {
    direction : input ;
! k4 ~4 J4 G& ^( r" U$ j  G4 b- K    capacitance : 0.001915;
/ P* J& h6 ^: \+ P. i    max_transition : 0.217000;
    clock : true;
    internal_power() {
      power(POWER_7x1) {
* n# o# E1 c; R2 [4 [( E! y" P        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
* D$ Z* w( r: r      }
    }

7 d8 D* e( T- B1 A
7 ]; N) x5 y. c$ ~- [( h% H, ?& \: bvalues值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎?

    min_pulse_width_high : 0.061268;
( |: x! ~  i$ q% `# ^    min_pulse_width_low  : 0.125320;

+ o; `) E. A9 g) G# B- hCLK Hi/Low的長度?
2 x( E# G! J' y! ?6 `; d9 l  }
6 n  ^6 b3 Q* V" \  ?$ j4 y' V}


) u+ Y, [* i3 P% d* a8 ^
1 }9 t) i7 A, L; d9 l( o; J, c9 |' D有觀念誤解的話希望幫忙修正..謝謝
7 L9 p" J3 x4 y( H) N& K' p
/ g% P9 X) W) g) z+ s! b[ 本帖最後由 霜淇淋 於 2009-9-17 02:03 AM 編輯 ]