|
Senior Physical Design Engineer
: \! w$ P" I5 V: M/ L0 \公 司:A famous IC company* v. o( L, w7 [
工作地点:南京
" X$ Q- x; ^( f& Q8 y8 F2 I- i/ A/ e; A3 D2 ]
Key Responsibilities
. N0 v( E, A. J6 C% O; p; y! y& @Depending on experience, key responsibilities will involve some of the following: ; a1 ]( n. j8 d9 L. }$ e
IC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification.
3 k' D7 ]+ i# I" ZAs a key member of physical design team, your will work on one of most advanced and the most complex chip designed.
/ i2 X0 @, I( v5 b7 B9 K7 eLeading a team of physical design engineers and resolving the technical related issues. / x! x( v0 u$ o$ A A* x
Crosstalk analysis, power analysis, and static timing analysis.
1 H/ y8 @: ~2 ?! YWrite scripts in Tcl to improve productivity. 1 f9 \# z( A4 d9 g
% E4 x0 o/ H2 ^+ O$ g/ H
Experience: 5+ years in physical implementation engineering
s6 g7 I, u- a& |. `9 p ( z$ K3 X& _& Z- v9 J% L
Essential skills / x) y/ {1 u, h( u4 ?0 A) l* G/ Q
MS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills 9 }& I1 Q9 V0 _ x3 q
Experience with Magma or Synopsys place-and-route tool set and physical design project implementation. & U3 |5 U! C' C- F9 W
Good programming skill. Capable of writing Tcl or Perl.
+ ?7 q- {& ^! M3 ^; f" KFamiliar with synthesis, static timing analysis.
9 o* [# l, p9 L% aSelf-motivated team worker, good verbal and written communication skills in English. 5 F- K H+ N; }5 f5 i
Technical and team leadership proffered. Previous management experience highly desired. $ i) h0 _6 t4 @
Experience with synthesis, DFT, and verification is preferred. |
|