A Layered Verification Approach Applied to an AMBA-Based System

phoenixfeng

It’s common knowledge that the verification
stage for a given system is
around 70% of the overall design
3 ]5 |" ~! s2 R7 v/ Seffort and schedule time. Reducing
overall time spent in test creation and
" ]* G& k( _3 q- G8 adesign verification is a high priority.
0 X! E, M8 x2 d' Q3 `Success in these two areas increases
productivity and helps deliver products
) ?% C& y% u/ d$ nto market faster. To achieve these verification
. X! X! k2 Q7 ^/ G& N( mgoals, engineers are constantly
looking for new and innovative ways to
7 k0 R+ ^0 n, {0 x+ fconquer the verification challenges that
' Q) W. [7 D2 Oface them.
This article discusses a layered verification
$ _0 @( w% r+ O0 _approach as applied to an AMBAbased
3 o8 g0 `9 p; vsystem component. The layered
2 N2 ^/ f2 l: l4 M6 \( sapproach is used to create a standardized
verification environment that can
7 p+ o. j! Z; @6 F. [7 G7 Uadapt as the design challenges
/ X9 \% l- q7 r* F( fincrease. Typically, reuse is very high
within an AMBA-based system because
* N) S" N- Q2 x3 i" tmany new designs are based on earlier
versions of the standard system. The
example shows the layered approach
being applied to verify an individual
3 X1 E4 v6 Z- cblock as well as its integration into the
+ U2 a  j* g( K  f9 y  E; L9 D+ fsubsystem and final system representation.

femark

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