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[經驗交流] 請教90/65奈米,SOC Tape-out一次NRE大約多少

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1#
發表於 2009-8-13 10:26:46 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
如題
' S) Q# n: Q' c$ O% z2 S
" U9 C" ]: q# ^2 ~9 p/ l請教業界各位先進
$ |+ G9 {9 Y( Z& R4 Y+ V$ b, o! p目前的chip開發,需要多少投資?
7 O0 i& S3 N. A4 E- r- _" l首先是假設 Febless design house.3 Y' L9 i$ Z+ s/ p9 X- p* K
自家由algorithm 到 RTL simulation 完成7 b7 r0 N  E+ {7 s" M  o
後端包給 backend service 公司 (layout, mask, Fab, assembly..)( L4 S+ F, T2 J2 R
以 ARM9 or ARM11, AMBA2.0 為platform
3 p" Z- S5 y) J( G6 `5 Q* g那麼
) C( }/ s+ j2 x  y8 t$ x6 D  (1)90奈米, NRE大概多少?
4 K" e, E3 o0 `' K& `, F- h- D7 C" z$ Y  (2)65奈米, NRE大概多少?- x0 N  g/ Q3 g% t8 [2 Q8 i
  (3)或是您知道其他製程, NRE大約多少...$ ?% c2 \4 ?; g' C/ h
3 H- b" ~6 v4 [% [7 n
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2#
發表於 2009-8-14 01:17:51 | 只看該作者
Which design service company you will go to?
9 T2 k* m5 A, G4 U" R* }How many mask layers it will be?
6 u4 i6 S- q9 \; f% \7 d! P' V2 Z* VBesides, ARM, any other IP, like DLL / PLL / EDRAM / USB / LVDS..... and who will be the IP provider(s), wafer Fab? design service companies? or 3rd parties?- Z; I( C6 k# r' H3 y8 q: \
How many chips you need? A full set mask or MPW?9 g) L3 O6 P" }/ G6 j
What package you need?
3#
 樓主| 發表於 2009-8-14 08:59:04 | 只看該作者
Well,
: t+ d# R& N' W
. j; E" ~# E( G  E* w6 |I just estimate the investiment of a ASIC team.
1 M1 U- z! T" U% I* w) snot servey for a project.: J2 E3 b/ `5 l& z4 f7 [
So, I just want to know the range of NRE.
/ t) w: l( q) Y" \2 g" I7 Y& G. W: \* a. Q3 |5 ]  R+ C
For example, It will be
3 R3 M" h7 T0 ~1 _(1) 5,000,000 NT$ ?
+ \$ w5 o3 [$ b$ r(2) 8,000,000 NT$ ?# d5 ?' y, O2 Q2 i% ?" Q; L
(3)10,000,000 NT$ ?- Z* z4 Y' @) w& v
(4)12,000,000 NT$ ?
1 w/ M0 p! ^& }: ~8 K(5)15,000,000 NT$ ?
/ b  c0 B' t, K  f) ^
# P. B( v5 s: X8 y/ e# w2 }$ h- |Sure, I understand following things:
% p/ ~6 p- V& i/ M2 C7 `2 Z - full set mask cost more
% X- p! J$ m. Z# |4 {0 e) m/ w, ` - PLL/LVDS... analog IP are extra cost: s: T* l. e; K! R6 p
- pin-count and area also influence cost2 a9 b" O5 g* k
- different package also cost different5 g" o7 z4 K6 R4 V" j' U2 O
! ?6 j' C  i# z% r
Therefore, if really need information for estimate,
3 y! X# V" X! Y* a! n1 ?9 \just for example.
& [( S# M, N4 ?' m4 U7 z) \Let's assume a SoC for FullHD TV application
. j9 @2 Z& Y, [: o8 Uit will include7 }; @$ d1 X1 J/ D) S6 j$ k
  - ARM AMBA- U/ e2 M: q! Q2 T" r; ^6 N* D4 |
  - DDR2 I/F
' V5 J& q, g. |8 ]! t  - GPIO, IIC,...
6 ?8 A' k7 q; [% q! R8 K6 ?! J  - LVDS out (dual link)
0 C2 i# x; p0 r0 r  @( x  - Video-in: HDMI(1.2)x2, VGA, YCbCr, A/V, S-V, SCART,* S1 e7 ~: b+ D: i8 E( i# Y" b
  - 12bit ADC, 10bot ADC x2$ Z( j7 D0 r; _
  - PLL/DLL3 q( V5 o9 b) n
  - 256 pins 以上
1 C0 A( ?3 w% Z
, T2 w0 g6 f" x" ]* x' S. x3 g3 P8 VThan,... any idea about NRE fee?
, O* w1 w( s2 M0 d# ~4 h' H3 G( w. Lagain, I just want to know the range
4#
發表於 2009-8-14 09:25:01 | 只看該作者
if the ARM and AMBA is hardcore,! J0 v& e1 a  _- d
basically 65nm-->USD$1M above and 90nm-->700K above
7 g( p- R& I$ Band base on different foundry has difference price!
5 Q! ^) P0 o7 P& e; I' Q2 qthis price did not include any specific IP like TV encoder, decoder, vedio codec....3 @6 j; _" ]( w3 l3 w
and did not include the ARM licensee...8 |( e: {% B! F
actually! it is not so much IC design in Taiwan tape out 65nm till now!
5#
發表於 2009-8-14 09:28:45 | 只看該作者
sorry, this price also did not include the shuttle or pilot run wafer(basically in 65nm will be USD$3xxx at 13pcs wafer)
- [6 M. x2 X  q4 N+ {8 c7 s; ^: |and package&testing, so you may count it at USD$1.3~1.5M if you are running turnkey solution!
6#
發表於 2009-10-22 11:06:45 | 只看該作者
need 1M dollar?
7#
發表於 2009-12-15 21:05:38 | 只看該作者

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