|
招聘公司:A famous IC company0 W0 Y8 t K# T9 ~
招聘岗位:ASIC CAD Engineer9 S7 n5 O4 }6 |# n# [
工作地点:Shanghai3 T e3 Q% N$ Y" [$ x4 b, R
" ^- b$ I# z! m0 Q岗位描述Description of the Role / Responsibilities:
/ |3 j0 C( y# T9 G) d8 e' @9 |* v' |9 z* _5 a
Participate in the design and implementation of the leading edge ASIC chip.
6 l& ]6 \6 F: HYour focus is on design flow
# F' }% F9 _# [7 U0 i5 ~# HEnsure the design methodology correct and improve automation and productivity. The main flow steps include: # v5 L: h( z" w" r" v3 j* d
FE: Synthesis, Simulation, STA, Design Check and memory compiler etc.
5 s' H! C6 K! }BE: Place and Routing, Physical verification, Signal integrity, Power analysis etc. " h+ @% f# d8 I0 X8 A9 d, ?2 L
Another important part of the job is doing support to FE /BE team. ) K3 P' j( q0 V4 s/ h" z
When they have a real design issue and can’t solved by themselves, you may be asked to jump in for debug and find a solution. Usually you will work with EDA vendors on such case.
, A, w6 L7 \ b& {! _5 e9 WResponsibilities besides support project work also include interfacing with other implementation experts across different development locations, and driving the continuous improvement of advanced implementation methods to Trident digital TV and Set-Top-Box projects teams.! K( n1 K( P7 [2 }: d1 E
$ W( a7 C, O, V" X# ?- j0 ^ E职位要求Experience and Skills Required:
! B! k( M9 q m% G9 @Essential
U4 B4 c6 M# E$ N) W8 C% f8 d9 m& {Major in Electronic Engineering or Computer Science.
0 g5 T( @$ ~- V6 e; q% QMaster (or Bachelor 2+ years related experience) ! X4 P% w' i# @( f* {( d6 S
Strong programming skill with one or more following items( Perl,Tcl, C/C++ etc).
1 |! G+ n$ [4 g2 ^, [2 C6 YExperience with industry standard development EDA tools and flow. & ^: C* X( e+ ^, p; |- b8 G5 U( S$ Q
FE engineer: DC, RTL Compiler, PT, Conformal LEC, NC. VCS ( B8 N: G7 j1 a5 y, p/ @) M7 M0 u$ w
BE engineer: SOC encounter, Apache Redhawk etc. 6 N8 H6 K* j' W& t& {2 l/ I# h
Good written and fluent oral English. 2 ]- v4 h& T4 e6 \
Good communication skills and team work.
0 v4 A# z9 R7 w2 d5 e8 | ^8 U: B5 H* i) ^8 K2 E
Desirable
4 E" G, s3 D y. S- TReal ASIC project experience as a FE or BE designer is a plus. |
|