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Staff Verification Engineer
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- f4 S9 y5 O) U- r公 司:one famous IC company( b7 e2 f2 f# L6 m5 I3 h
工作地点:上海
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- h) L$ C- z5 j8 u/ ZQualifications
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Minimum of five years experience.
( g" W) v7 ?, F P4 e: |" aAdditional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
1 O5 z3 I2 ] g( ~Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology. - X% J' {! ~9 P/ V7 \/ d* v
Candidate should be familiar with industry standard ASIC design and verification tools and flow.
" O1 ~/ c: i9 IGood knowledge ddr protocol and computer system achitecture would be an added advantage. 0 a1 z* A3 H: G% Q
Good knowledge of Perl and shell programming would be an added advantage.
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Responsibilities: 1 T6 y, ?' d% ~! a0 M
-Understanding the expected functionality of designs. J. G) h$ \* w# h5 O, J
-Developing testing and regression plans. 5 h0 Q, b" f( n6 k& r$ M0 Q5 `
-Designing and developing verification environment. 0 ~' j! `! F" p" b
-Running RTL and gate-level simulations/regression. 8 y. q" U0 G% ?
-Code/functional coverage development, analysis and closure.; h, ?% X/ F5 ?1 w0 `9 _; g
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Requirements:
) o0 o& q# ~& H5 [6 [Experience & Skill: 5 Years
9 W6 @( }! n/ r; i# z-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
" R7 b' \) \& J% d5 K-Knowledge in ASIC/FPGA design process and verification tools. 7 u1 k5 V5 Y' c. s
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.). 4 D, A! Z& A5 g* G9 G6 F# L4 v
- Scripting and automation skills (tcl, perl, makefile etc) a plus.
5 b4 U& m9 ?, ]-Familiar with C/C++. 3 O0 C' u4 \/ T/ U
-Knowledge of DDR protocol a plus. 5 ?- l; H1 [" D+ w9 u0 L
-Independent and self-managing. |
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