|
Sr. ASIC Design Engineer (encoder/decoder): ^! x! B3 _4 s4 \; J$ A8 T
, d# ?6 j/ W5 A$ |4 I3 [公 司:a leading developer of advanced digital imaging solution: j( O# B. J3 X
工作地点:上海0 z! V, Y. d; _- U; y) R; ]
# o' U% W3 }6 V9 w4 x) C) R" c+ b
Position Overview: The candidate will join a team of highly competent ASIC designers involved in design, verification, and implementation (ASIC) of advanced platform for XX''s future generation multi-media products.
! p* U, p" S: B0 e7 ?6 F# S* z$ m; L2 {- T+ l
主要职责 (70%)
6 P! P0 _8 c" qIn-depth knowledge of TV encoder and decoder design. Good understanding of TV system design. 8 L, }! Z K: C# `
Proficiency on digital filter algorithms and hardware implementation. * b8 @* B) S! a, e6 ]4 V7 e
Development and verification of complex IP module, integration of the IP module into the Soc devices, top-level design handling, system level testing. ! m6 |/ y0 G3 D; S
Participate in the FPGA platform development and lab debugging 8 k( h) }" m3 n( R2 g: b3 H( ]2 l
9 Z( ^/ |, I4 W. O* x! [5 \其他职责 (30%)
; M4 \7 r: _# g0 L! K3 i) c2 C1 |Participate in block level architecture design Assisting embedded FW development.: U# Q" ^) _9 b& t6 O X
职位要求
2 U% a/ P8 {& W. U+ T' z! B: S9 z岗位资格 : U8 ]% k$ [ b" e; H
经验/技能 1 s' t: W, f9 }
1. Strong knowledge of TV technologies, knowledge of image signal process and CCTV system is a plus ' B( ?0 y8 ^$ N9 Q
2. Strong knowledge of ASIC design flow. Can define Micro-architecture of the IP module and /or sub-blocks. And able to write detailed engineering specifications. . @' d. y; `8 T# M
3. Good communication skills, especially in technical writing and reporting;
5 E# O9 E; _' ]4 v4. Self-motivated and ability to excel in a team environment. 2 w( o7 z4 C- N4 z: v k4 g2 v
6 E4 T; ~ [, @6 {2 a' W9 R. i
教育
. V- F. K9 g) h4 F* gMSEE/CE with 3+ years of industry experience |
|