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Staff Verification Engineer
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6 I2 S0 u" K& g公 司:one famous IC company
- L: x- j- v9 I6 t工作地点:上海" C7 L. @0 I8 \3 [+ `
# E5 v; X5 A! zQualifications
: i3 I- P* Q/ B( F/ ?) y; D# HMS in EE/CS/ME. 1 a' ~5 }& d, ^3 y. f! G/ \
Minimum of five years experience. $ P, |2 r! `( |- t: M" [- u, t) V* N- R
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.8 t1 e6 k. H2 o
Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
) \, `& h; T7 G, ?9 e% j1 uCandidate should be familiar with industry standard ASIC design and verification tools and flow. I0 [8 R% w- v7 ]! d4 h
Good knowledge ddr protocol and computer system achitecture would be an added advantage. 7 j, E o( d$ _1 ^! Z0 x9 A
Good knowledge of Perl and shell programming would be an added advantage.
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0 C5 l; ? }! O% w( U/ w( e- aResponsibilities: ) ]9 ~1 y2 y0 P2 h2 n! B
-Understanding the expected functionality of designs.
8 u2 V8 w* ^, `* o$ ^; W-Developing testing and regression plans.
6 ]( ]2 C9 q* K-Designing and developing verification environment. + |$ y& I q% \3 ?& o0 s! ?
-Running RTL and gate-level simulations/regression.
* T$ a6 u9 t4 W$ u, B* d( q-Code/functional coverage development, analysis and closure.
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: Z2 ^9 f; h( u( fRequirements:
1 d/ ]/ C" K" y( u C8 aExperience & Skill: 5 Years
2 }8 h. U' b. V" j+ n. j-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
# H' z" b+ s5 F- n( }# V-Knowledge in ASIC/FPGA design process and verification tools. ! z# A2 c4 O. i5 Z1 y
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.). ) v3 u1 s" b1 p, \ w P6 J8 h0 y
- Scripting and automation skills (tcl, perl, makefile etc) a plus. % g o% N. u' Y! J
-Familiar with C/C++. # y6 ?: l9 D# W: y9 w+ Q
-Knowledge of DDR protocol a plus.
8 k* I% V* z7 C$ t6 l-Independent and self-managing. |
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