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Junior Physical Design Engineer
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! u' s: R) n0 C" E% ~# R公 司: famous IC company
: c8 p5 t% U7 \工作地点:北京
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Position Tasks, Duties and Responsibilities
% ?8 l, T% ?6 T8 l' @( xThe ASIC Physical Design Engineer will: # ^$ D8 |; \) u
Complete third party IP integration and ensure vendor guidelines are followed.
3 U& s. h# |, V, O4 d( x Responsible for physical verification (DRC/LVS). " q# I" g+ }5 a1 [
IO ring design, fullchip floorplan. # f7 N& Y' f5 N. W% n3 d, w
Block level implementation.
& t" G" o2 c; U d) z5 P1 C Work with front-end engineers to resolve problems and achieve design closure. + w2 u3 ?# w6 Q d) V6 h' v; ]. H
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Candidate Qualifications:
( R, h/ H; Q7 QCandidate must:
, k* s( P H6 y9 S7 N, m/ p! r$ p Hold BSEE (MS preferred). 3 S+ W$ j$ B* R8 c7 ?
Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification : ~6 P" \5 m* o) K' F `
Be able to complete block and chip level tapeout quality LVS and LVS and DRC.
! h; y* z2 o# G- F Have the ability to independently identify and resolve design, tool, and flow problems.
" k8 s% ~( [/ T' q+ [' Q- m Have related timing and physical concept.
2 {5 A- b/ {3 _7 ?8 U2 p Be able to design and implement physical design strategies and methodologies for deep submicron designs.; p* k. G. v/ v
Familiar with EDA tools.
$ |: c7 f$ q4 j" Y: e Familiar with Linux environments.
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Any of the following is beneficial:
" H3 B" u5 A, }+ y, E9 Q STA constraint design
% b9 q9 l! V" T2 r0 Q Equivalence checking ?RTL to gates, and gates to gates. |
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