hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs
& r5 V# D! A9 g$ U6 S
- \$ B; Q7 _& @: H$ ^) z/ e要怎麼定義用
8 z5 ^  j% ^# j& h4 Qplot LX??

( k5 v& b7 J" I. R  C請各位幫忙一下

小朱仔

直接下.op及.probe
找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .

3 v2 c0 q4 |* y0 t  `5 nCgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.


For your reference.

0918429587

CAB_BS    LX28
CAB_BD   LX29

9 B; X& j- R- I/ y* y其他我找不到
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
這是 CGDBO  CGSBO CBGBO

不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
8 j! Y" I! W2 A' i4 Z) rAn example for your reference...
% K9 V# k( `0 ?" A+ T7 t9 Q' V- Q; d
& D8 c7 X. K3 P* D3 k----------------------------------------------------------------
***** Gate Capacitance Plots *****
6 \( ]. M! _- d.lib 'your_component_model' lib_corner
8 L6 x6 k, x5 F& Y( t  L0 U* X' F.temp operational_temp
.option dccap=1 post
m1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
) K# _  u. }! K' [+ Fvd n_drain gnd 0
vg n_gate gnd 5
" l# y: T# m0 F, wvb n_bulk gnd 0
4 P, q/ R% G  G9 R& ]) I: C3 t.dc vd 0 5.0 0.1
.print   CGG=lx18(m1)
6 C1 K% J$ N% k0 \$ b8 @+        CGD=par('-lx19(m1)')
+        CGS=par('-lx20(m1)')
& R1 T; h% Q, T$ g; z* k+        CDG=par('-lx32(m1)')
+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
" P# K! T6 P- e7 G  Y" A.ends
  C# l- Q$ g+ N0 k
----------------------------------------------------------------
) c1 W; \0 V% q9 \Six capacitance are reported in the operating point printout
: e7 W9 G% d5 z  u) o7 Q2 l    cd_total = dQD/dVD
/ x! A6 c/ q/ W0 o8 O+ n* g! M    cg_total = dQG/dVG
/ J4 q9 \% O0 T( P& w& @- J  n    cs_total = dQS/dVS
4 z  `9 [+ i! J3 m! [9 [    cb_total = dQB/dVB
    cgs = -dQG/dVS
3 O  H2 C6 C+ t    cgd = -dQG/dVD
There capcitances include gate-drain, gate-source, and gate-bulk
/ w3 `. o/ @/ r* u. i; r+ [& f8 d! Joverlap capacitance, and drain-bulk and source-bulk diode capacitance.

1 G6 H+ L, ^- H8 ^- H+ ~$ B! i4 UCGG = dQg/dVG
CGD = -dQg/dVD
  r9 T1 i3 W4 f2 i2 W# `+ q0 sCDG = -dQD/dVG
2 z% @% J! j% q- |6 j2 e  j' [
The MOS element template printouts for gate capacitance are LX18~LX23
and LX32~LX34.
( P) o: V) @; m4 _9 A
LX18(m) = dQG/dVGB = CGGBO
- L' }! w: X0 f6 uLX19(m) = dQG/dVDB = CGDBO
0 |# y9 c$ U+ RLX20(m) = dQG/dVSB = CGSBO
; }4 ?' q. E% V9 a  i
LX21(m) = dQB/dVGB = CGGBO
LX22(m) = dQB/dVDB = CGGBO
LX23(m) = dQB/dVSB = CGGBO

LX32(m) = dQD/dVG = CDGBO
7 c% l1 ~, {4 X7 ~LX33(m) = dQD/dVD = CDDBO
LX34(m) = dQD/dVS = CDSBO
! o& E* s; _) o( Q2 I0 x
The equation shown above is for an NMOS with source-bulk grounded
configuration. Refer to the user's manual for more detail ^^