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Configuration Management Engineer (Digital IC Design)請進來交流!

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1#
發表於 2011-7-20 12:12:57 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
招聘公司:A famous IC company( O" D# g: s$ r' x% P2 {# ~
招聘岗位:(Senior) Configuration Management Engineer (Digital IC Design)3 O9 k% a$ ]; K6 M$ Q9 {
工作地点:Shanghai; Y1 @& i6 n7 {2 C( ?6 [

/ P* M4 B4 y7 n岗位描述:
' B9 g" [; l. p/ BDuties · Do database management/configuration management to support Digital SOC product development for mobile phones · Administrate Clearcase /DesignSync · Administrate change control and bug tracking tools · Do linux/LSF compute farm/ CAD tool first-level support to Digital SOC design team and interface to company IT/CAD organization · Take charge of CAD investment request consolidation
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! l3 P9 v4 a) w; X职位要求:1 v, D# ]  W' p# D
Requirements · B.Sc. degree or above in Semiconductor, Electronics Engineering areas · 2 years or above experience in Clearcase/DesignSync administration and configuration management in Digital IC Design domain · Good knowledge of digital SOC design is a big plus · Good knowledge of linux, LSF compute farm and script writing (e.g. C shell, Perl) · Good communication skill, will have frequent communication with foreign teams. · Good written and spoken English is mandatory.
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: X3 `+ M& S! Q. E9 p能者與意者請email研發簡歷與chip123聯絡。
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2#
 樓主| 發表於 2011-7-20 12:15:58 | 只看該作者
招聘公司:A famous IC company' I. b- i2 @8 [9 ?
招聘岗位:(Senior) Digital IC Design Engineer (FE Design)9 d& J* D: r) [1 L$ H# y) Z
工作地点:Shanghai
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岗位描述:2 i8 D: w% P* ~8 X3 y9 P& C
Duties • IP design and support for digital baseband of cellular phones • Digital SOC design and integration for chips/ ~- N  D" ?1 D5 ^* G" d" q
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职位要求:6 @, C$ a! ]" O1 C. s# ^
Requirements • B.Sc. degree or above in Semiconductor, Electronics Engineering areas • 2 years or above design experience in industry • Good knowledge of design flow including documentation, VHDL/verilog coding, code check, equivalence check, synthesis, timing analysis and RTL simulation. • Good knowledge of AMBA AHB/AXI protocol is preferred. • Good knowledge in UPF/IP-XACT based design flow is a big plus. • Hands on experience in digital IC design EDA tools, such as NCSim/Questasim, Design Compiler, Formality, Primetime etc. • Good communication skill, will have frequent communication with foreign teams. • Good written and spoken English is mandatory.
3#
發表於 2012-4-16 11:36:53 | 只看該作者

Staff Engineer for Digital MAC Design

客户 A famous IC company  F* Q- C- K% N* Q- R
地点 Shangha
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3 I$ H/ e2 I' z职位描述8 a4 Z4 X9 v) i, y2 ~
We are looking for a person to join a design team to execute a state-of-the-art IC design project in the wireless communication field. Candidate must be familiar with digital IC design flow with a proven record of design and verification of a complex design project that led to successful silicon. Proficiency in Verilog is required.
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) Z4 z! e; `' \. Y7 b职位要求
& R' Z  W# y7 O2 ~Requirements:
0 Q) V; D6 b( QExperience in the following areas of expertise is desired:7 A: y& ?  k% B3 L' @, d* C  C
Wireless media access control (MAC) design experience would be highly desirable
# P+ w$ L. E! }* K' ?" I4 e; B8 XKnowledge of TCP/IP and DMA Offload Engine design experience will be a plus' t' `8 f. ~: Y0 i& d  G/ f
RTL design, verification, and chip integration
: ]% v# u' ^  ~8 J8 vExperience in the following is beneficial but not necessary requirement:
) L, d  c& M2 U% ICommunication systems and RF systems
. Q! T5 }3 Q( j, wFamiliarity with wireless communication systems and standards (802.11b/g/n and WiGig)2 z5 `' c: I# O, q% v# [: ^% K
Knowledge of interface protocols such as PCI/PCIe would be a plus7 ~) z4 l& u% L& I0 y$ }
FPGA design flow, testing, and emulation bringup& H3 n* B, V& x6 j) I

7 m/ ^6 J: @% _: `3 aOther requirements:
$ n" `- F1 I9 P3 s' ]' wFamiliar with design and verification languages, EDA tools and ASIC/SOC design methodology( D0 F; Y8 {: G8 ~9 H
Good script language skill, such as Perl, Tcl and Shell; # ?6 t# n: m- h7 M1 k
Good written and oral communication skills in English; 0 y9 b3 @9 b4 c8 R# h( m9 N+ V  [
Good Team player+ r0 U# Z& ?: R" B1 w7 {9 L
Candidates must have MSEE degree with at least 5 years of experience
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