關於cell-based 流程的DRC問題

ywchywch

請問各位大大
& q) K' a; M: _6 i我用TSMC18的design kit作cell-based layout的練習，軟體是用encounter，大部分的步驟是依照CIC所提供的Lab去做，完成之後用我的GDS檔去做DRC，會出現下列的DRC ERROR，而且是M1~M5、via1~via5都會有這方面的error，因為error的數目頗大，不太可能用人工去debug，所以我想請問有經驗的大大們，能不能告訴我最大的問題點在哪裡？以及這些錯誤代表什麼？要如何debug比較適合？

8 }# R3 E9 K, r( l先謝謝各位大大了!!感激不盡!!

1. M2.W.1 { @ M2 width < 0.28
$ ^! J" a3 R% `) H) B  INT M2 < 0.28 SINGULAR REGION ABUT < 90
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6 N  ~) M# x2 A2. M2.S.1 { @ M2 spacing < 0.28
  EXT M2 < 0.28 ABUT < 90 SINGULAR REGION
}

# _( k, c$ I, y  a0 t3 R% n3. M2.S.2 { @ Wide M2 (>10um) min. to M2 < 0.6 um
  M2_S5 = SHRINK (SHRINK (SHRINK (SHRINK M2 RIGHT BY 5) LEFT BY 5) TOP BY 5) BOTTOM BY 5
! r3 u+ U" A" b  Z8 q  M2_G5 = GROW (GROW (GROW (GROW M2_S5 RIGHT BY 5) LEFT BY 5) TOP BY 5) BOTTOM BY 5
  M2_Wide = M2_G5 AND M2

0 T4 T8 ?" D" b5 n. G" }  M2_Exp = SIZE M2_Wide BY 1 INSIDE OF M2 STEP 0.196
  M2_Branch = M2_Exp NOT M2_Wide
$ B7 w. }' K2 N/ ~# H( Z/ V  M2_Branch_edge = M2_Branch COIN INSIDE EDGE M2
2 @. x* g* V& m  M2_Check = M2 AND (SIZE M2_Exp BY 0.6)
! ]3 H7 H" e* T2 O& a' u0 J  M2_Else = M2_Check NOT INTERACT M2_Exp
3 H7 U) f6 x) k6 G, ^7 Q& M  M2_Extend = M2_Check NOT M2_Exp

& j% R/ H+ ]- U5 d: {4 X  EXT M2_Wide M2_Else < 0.6 ABUT >0 <89.5 REGION
" H* T" V2 `( u2 F  EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 OPPOSITE REGION
  EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 CORNER REGION
  EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 PROJ==0 REGION
' h! a2 l/ i9 j/ M  A = EXT M2_Exp < 0.6 ABUT > 0 < 89.5 SPACE REGION
2 {; r# X4 Y' T  A NOT INTERACT M2_Extend
}
4. M2.E.1 { @ Min extension of a M2 region beyond a VIA1 region is 0.01 um
  T. y; s$ G9 `  J* D5 V6 a& ?   ENC VIA1 M2 < 0.01 ABUT<90 SINGULAR
1 A  c9 J* U' l   VIA1 NOT M2   
}

2 R: p* u) T0 w! j5. M2.E.2 { @ Min extension of M2 end-of-line region beyond VIA1 region is 0.06um
   X = ENC [VIA1] M2 < 0.06 ABUT < 90 OPPOSITE                // a narrow side
- P* P% k! H; R8 _; C1 q   INT X < 0.26 ABUT == 90 INTERSECTING ONLY       // adjacent narrow sides
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/ O, ]- `) g3 M( }1 {
* E! }1 C. ]' e4 a4 Q6. M2.A.1{ @ Min M2 area region < 0.202
2 ~# g" H8 w) S+ I+ y  AREA M2 < 0.202
$ e! u% }& c9 m}
// Density check M2.R.1 included at the end of this file
// VIA2 checks
//=============
& R5 l) {' l! q& ^
7. VIA2.W.1 { @ VIA2 must be 0.26 x 0.26 um
  A = NOT RECTANGLE VIA2 == 0.26 BY == 0.26 ORTHOGONAL ONLY
* M& f/ X4 H/ e# K& [6 i6 c  A OUTSIDE RNGX   // exclude from metal fuse protection ring area
9 t+ T$ ~3 S4 e+ Y4 ?* b}
  b$ N* o. l8 X9 c
8. VIA2.S.1 { @ VIA2 SPACING < 0.26
$ S4 f* Z# ~9 i/ W  EXT VIA2 < 0.26 ABUT < 90 SINGULAR REGION
}
: }9 e! p1 e: q* O
9. VIA2.E.1 { @ Min extension of a M2 region beyond a VIA2 region is 0.01 um
* o0 w- z4 C" N4 G& k  ENC VIA2 M2 < 0.01 ABUT<90 SINGULAR
9 j" R8 r- R; h/ |& j' ?  VIA2 NOT M2   
& f- j$ g% a/ `0 [1 V}
/ J. [, k8 _- A, `
10. VIA2.E.2 { @ Min extension of M2 end-of-line region beyond VIA2 region is 0.06 um
   X = ENC [VIA2] M2 < 0.06 ABUT < 90 OPPOSITE         // a narrow side
   INT X < 0.26  ABUT == 90 INTERSECTING ONLY     // adjacent narrow sides
' E6 k+ |6 }7 Z1 N4 T}

motofatfat

我猜你試用APR軟體RUN出來ㄉ
應該是相同NET ㄉMetal space 和 via extension
. S) @: }1 s: S5 l7 e4 Y不夠的問題,通常會用 skill file 來修正

michael6172

我覺得你打電話去CIC問工程師會比較快吧 ...