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樓主 |
發表於 2010-1-13 11:54:47
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回復 5# daidai # U9 k4 F+ H. X( _
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Thanks, daidai.3 f: C X3 V& e0 m8 {/ I9 K7 U
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But I don't think that no need clamp when using P/N MOS, i.e:; x1 D( l* B$ ?! q# w
Suppose there is a pad A which voltage range is vss ~ vdd, when zap vdd vs. padA with positive pulse, the current is only be discharged by the reverse parasitic diode of gdpmos, the turn on voltage of this diode will be too higher to discharge the current quickly, then the internal circuit may be destroyed. |
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