|
4#
樓主 |
發表於 2013-12-12 09:14:21
|
只看該作者
Senior Physical Design Engineer! L) w3 e- f/ w4 R* \0 F/ x
公 司:A famous IC company
! Y" h/ n1 \6 R4 i0 ?" z. h7 `工作地点:南京$ e4 l" |' ^: m, D1 u t- [
6 b! y- w) f' |6 V6 J2 g( W: W
Key Responsibilities 5 ^; O ?. y: ^9 |0 n
Depending on experience, key responsibilities will involve some of the following: + N, ^( {( ?' t
IC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification.
! f$ U2 ^% X" j4 x' uAs a key member of physical design team, your will work on one of most advanced and the most complex chip designed.
6 X" ]: ^, y8 w& A4 V' L( E* OLeading a team of physical design engineers and resolving the technical related issues. s# i' M/ b% m2 Y% {' M
Crosstalk analysis, power analysis, and static timing analysis.
' U$ u3 _0 v( b$ J- R6 s, uWrite scripts in Tcl to improve productivity.
; o& c# z- }! Z$ d9 r9 R4 r2 N) [- X: e1 ~1 b" V
职位要求0 v3 r$ }; L5 U* \+ S: M0 m
Experience: 5+ years in physical implementation engineering ) P# [' B1 Z% Z2 n
Essential skills 3 c/ S9 Z1 ]- a+ q
MS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills 4 ?5 g s. C1 s; r+ t$ m
Experience with Magma or Synopsys place-and-route tool set and physical design project implementation. ( S3 e1 t8 J; n
Good programming skill. Capable of writing Tcl or Perl. % `' H6 g) Z( b, @9 V3 H+ [
Familiar with synthesis, static timing analysis.
; M& {7 v4 w0 Q! }* e" Q: K8 z4 jSelf-motivated team worker, good verbal and written communication skills in English.
5 y4 N% C) B) k; T' L9 ~4 ~, B& `Technical and team leadership proffered. Previous management experience highly desired.
# ?5 O6 ~6 d d0 zExperience with synthesis, DFT, and verification is preferred. |
|