[急]verilog pipeline bubble 設計

HsuanChihCh@FB · 發表於 2016-10-19 23:25:35

我目前在設計一個pipeline的電路，且有防bubble機制，但在設計的過程中有些問題~
想請問一下大家!!
該怎麼設計?
以下是我需要的功能~

Module name	my_pipeline
Signal	Direction	Description
clk	input	System clock
rst_n	input	reset signal, active low
d_in[15:0]	input	DUT input data
d_rdy	input	DUT input data ready
d_full	input	The next stage data full signal
pp_d[15:0]	output	DUT output data
pp_rdy	output	DUT output data ready
pp_full	output	DUT full signal to preceding stage

Thereare 5 pipe stages in our pipelining design.
It means that the input data can beobserved at the output port after 5 clock cycles.
All the stages must be readyto proceed at the same time.
When d_full is active, you have to keep the outputdata until d_full is disabled.
If d_full is active and all the pipe stages arebusy, you have to generate pp_full to inform the preceding stages to hold data.
The pipeline bubbles haveto be eliminated when d_full is active.

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[問題求助] [急]verilog pipeline bubble 設計