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[經驗交流] 請教90/65奈米,SOC Tape-out一次NRE大約多少

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1#
發表於 2009-8-13 10:26:46 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
如題
. X  K# O0 Q% i9 N/ p8 J. \: @1 b) N( x' O+ G/ f9 }" V  @( _
請教業界各位先進
/ [# l; c6 M/ l5 g$ `& _( L& c) D0 k0 _目前的chip開發,需要多少投資?
' w1 v% ^5 c7 b  W: ]  n; W首先是假設 Febless design house.
9 S' ~$ E+ ?. c" a8 n% N3 }自家由algorithm 到 RTL simulation 完成
" J) @( x1 V. U; \* x後端包給 backend service 公司 (layout, mask, Fab, assembly..)
" \$ x# }! P/ g以 ARM9 or ARM11, AMBA2.0 為platform
1 B; z! @+ h' s8 J9 D; d$ m那麼
% [9 G0 e' I7 d& z. l9 |  (1)90奈米, NRE大概多少?
7 F1 ^/ U2 t" d( W$ e  (2)65奈米, NRE大概多少?, q& M( M! z. a$ `' [
  (3)或是您知道其他製程, NRE大約多少...) `3 [% G" w( Q
: X( v& s, D3 t/ a
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2#
發表於 2009-8-14 01:17:51 | 只看該作者
Which design service company you will go to?
2 S& r' G. Q" H3 p" J/ y1 h, SHow many mask layers it will be?
- G- p1 ^$ t$ Y. R( FBesides, ARM, any other IP, like DLL / PLL / EDRAM / USB / LVDS..... and who will be the IP provider(s), wafer Fab? design service companies? or 3rd parties?
* z/ e! F. m& p) FHow many chips you need? A full set mask or MPW?: A/ R0 j1 a9 n( k* q
What package you need?
3#
 樓主| 發表於 2009-8-14 08:59:04 | 只看該作者
Well,
1 }  G' N: C) a1 @9 f% N1 ^! N6 _6 s
: H  F3 ~( U% j1 S  |2 {" p. pI just estimate the investiment of a ASIC team.
3 r" n& K+ ~! \not servey for a project.( T& y4 X) N# k! x7 v7 U- a" w$ p
So, I just want to know the range of NRE.1 G# h# ]+ g0 Y; }% [9 V

, x6 v) j# \" g  r. q) O+ n: rFor example, It will be
  A( L- {$ `% t! F/ D(1) 5,000,000 NT$ ?
7 v2 p. K* X2 F(2) 8,000,000 NT$ ?# H( x7 ]3 |1 i. J9 h2 e
(3)10,000,000 NT$ ?
+ @5 r' e. K8 o7 c(4)12,000,000 NT$ ?
. m" |4 x3 W' C, Q: G8 H9 }(5)15,000,000 NT$ ?
, y& p" H- J! r5 s  K' O" a) P4 @3 f! g5 w* R, ?& Q: r
Sure, I understand following things:5 X) P/ P  T3 T+ @  _
- full set mask cost more% k5 m9 Q) r& r; A$ W
- PLL/LVDS... analog IP are extra cost# ?' x  d! k) u3 K1 r: Y
- pin-count and area also influence cost
, e8 Z( j4 n8 C+ g - different package also cost different- q4 f0 s- j+ m% _
; a" {: b) F  W6 S
Therefore, if really need information for estimate," t; W# H4 n$ q: c2 K6 l( M
just for example.
1 z' n. X$ o1 V) qLet's assume a SoC for FullHD TV application" o4 i& t8 d5 Y& ?
it will include2 R) C1 o' A( Q' t/ O% y
  - ARM AMBA6 V0 Z) g: b  b0 y2 q2 f3 O
  - DDR2 I/F5 K; Q9 c: d- o* }5 o, D: X
  - GPIO, IIC,...
/ v/ H7 d& ?# B  e9 E- Y6 ~$ q  - LVDS out (dual link)7 o$ `9 z3 E+ `$ X2 Q
  - Video-in: HDMI(1.2)x2, VGA, YCbCr, A/V, S-V, SCART,
0 l- h) E4 a0 K; J& U6 i# {- p  - 12bit ADC, 10bot ADC x2
1 q4 ?4 L/ l  |8 l' S) @8 h  - PLL/DLL- M( ~* \( Y1 |' U
  - 256 pins 以上# y8 [! z! ~$ X4 y- Q
% m; X9 u/ B' `/ g7 ^: R* ?
Than,... any idea about NRE fee?
, L# n& f$ f2 sagain, I just want to know the range
4#
發表於 2009-8-14 09:25:01 | 只看該作者
if the ARM and AMBA is hardcore,
2 [( }! l& K: H- Tbasically 65nm-->USD$1M above and 90nm-->700K above2 k# y9 k, X$ J, w
and base on different foundry has difference price!
3 Y& T  I, m- \this price did not include any specific IP like TV encoder, decoder, vedio codec....6 q2 V: W4 O5 M
and did not include the ARM licensee...
7 w9 w/ ^  `( Z9 g6 Cactually! it is not so much IC design in Taiwan tape out 65nm till now!
5#
發表於 2009-8-14 09:28:45 | 只看該作者
sorry, this price also did not include the shuttle or pilot run wafer(basically in 65nm will be USD$3xxx at 13pcs wafer)! H, c6 z' B: a1 _
and package&testing, so you may count it at USD$1.3~1.5M if you are running turnkey solution!
6#
發表於 2009-10-22 11:06:45 | 只看該作者
need 1M dollar?
7#
發表於 2009-12-15 21:05:38 | 只看該作者

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