標題: DLL question [打印本頁] 作者: gavin114 時間: 2009-2-6 02:53 PM 標題: DLL question I am designing a DLL project, working range is 40MHz~240MHz, but the duty cycle of input clock is 40%~60%.' B- c$ x2 A% c$ H8 f1 e: ^ D
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1), in order to lock correctly, the delay will be forced to below 1 period when initial. so i plan to reset the vcntrl to be VDD?, E! D) ]+ ~4 k
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2), for the the working range, I plan to use voltage self_biased to make the charge pump?* X: ]/ ]1 M% _0 D+ b9 n
+ C( l; p+ k: {/ ?3), I preferred to use the differential delay cell, but the input clock is single ended clock with bad duty cycle, so plan to use invert chain to be the VCDL, the control voltage is connected to a regulated buffer to control the delay. 2 E- W2 `; V% v5 r( t" U7 z & w N& p7 w4 A- O) g) QHope anyone give me some suggestion. and is there anything should be concerned? and how to decide the Capacitor size? also according to the formula: Wn/Wref<1/20? based on the paper of "low-jitter process-independent DLL and PLL based on self-biased techniques" and "Adaptive bandwidth DLLs and PLLs using regulated Supply CMOS Buffres", Wn/Wref=x/4pi *(Cb/C1), where x is the scaling factor(multiple x of the regulate buffer current) in Charge pump. Assume the Wn/Wref=1/20, Cb=1pF, C1=20pF, x=4pi, which means the charge pump is huge. But the Capacitor 20 pF is already quite small? Am calculation is correct or not? thank you.. z! j' I# S9 l- Y3 r8 ^5 G
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4) if i want to use differential delay cell, should i need a duty cycle correct in the clock input? what kind of architecture can adjust the clock 40MHz~240MHz with duty cycle 30%~70% or 40%~60%.* d- \/ @( h7 t' ^9 d( S0 X
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Thank you very much[attach]6379[/attach][attach]6380[/attach]. l8 r/ o3 z3 A& `