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標題: IP development & verification engineer/AM 請進來交流最難職位任職要求! [打印本頁]

作者: tk02561    時間: 2011-7-20 01:45 PM
標題: IP development & verification engineer/AM 請進來交流最難職位任職要求!
招聘公司:A famous IC company" {; N- V  Z* t' V
工作地點:Chengdu% L. V" m, i) _* P! M0 K
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崗位職責描述:
1 \( J2 I; b! l9 @1. IP整合,合成,驗證和修正;* ?6 Y$ f0 d3 J% p  I7 {
2. FPGA平臺的搭建及基於FPGA的系統驗證;' }9 V' I+ B% d& m. Q$ v
6 _) Q0 M- R  l, \# e
職位任職要求:, w$ g4 `# D- ^5 b2 z) ]
1. 微電子/電子工程或相關專業本科、碩士及以上學歷;
( Z' T1 R! S6 M2. 良好的數位電路設計及模擬技能;/ T) I9 k+ `4 ]& c4 H
3. 有在FPGA上通過Verilog語言開發及驗證IP的經驗;; ^+ o1 [5 J8 _
4. 有digital video processing(數位視訊處理) IP開發及驗證經驗者優先;
/ ?/ i7 K) _$ T4 y2 w$ V* [5. 有C/C++/Matlab設計技能者優先。
作者: ranica    時間: 2011-7-28 11:54 AM
招聘公司:A famous IC company
# K+ q9 c& O; y: G2 t1 L' T! h! o招聘岗位:VLSI Sr SOC Engineer
! f9 z5 Y, U" y/ w7 p) W) n" \3 M& S工作地点:shanghai
5 @& [! S4 v2 D: l; I
8 K3 E) v" y( V9 c/ F岗位描述:Job Responsibilities:
1 k; D$ e1 A$ M, R, c' Y( O/ ~Reporting to the SoC manager, the candidate is expected to be responsible for following tasks:
; E2 v# M2 s8 X( S2 |& |* g- Develop state of art 45nm complex media processor SoC products with embedded cpu, memory controller, media processor and various mixed signal IPs" p  }$ C8 V* W' }3 T$ E* I1 N, n
- Work with other cross functional teams in China and overseas to specify, design, validate and improve SoC quality and timeliness to production
% y- i/ g  _% [2 d/ m( \7 D- Participate in SoC architecture definition, SoC integration and verification
/ y+ T- |* I) X) U4 t- Create and optimize DFT structure, STA constraints, pad & package selection% }5 }& I- B& _+ ^+ _
- Work with physical design team to ensure a successfully implementation until tape-out by performing RTL rule check, LEC and power analysis etc
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2 `  `9 p4 ^+ K5 o7 N. _! Q职位要求:Job Requirements:
+ k* @, r9 i0 O9 G7 q& s) @+ Bachelor degree in Electrical Engineering or related area, MSEE is preferred./ A9 A3 a, [  X1 g' r8 f
+ 3 years or above experience in ASIC/complex SoC design or verification.
( f! |# Y: J4 V+ Familiar with hardware description languages such as Verilog, System Verilog and VHDL  q! @8 @. A# G0 u/ G
+ Knowledge of script language, such as Tcl, Python, Perl are required4 F! D9 u9 D7 y) N" q& [
+ Familiar with IC design & verification tool flow with hands-on experience in DC, PT, NC-Sim and/or Spyglass
4 ?- G. ]6 ^+ A# _  F+ h4 f+ Good English and communication skills; will need frequent communication with foreign team.
! m$ k- L3 z3 P8 }+ Experience related to video/audio decoding, process technology and reliability qualification is a plus
作者: ranica    時間: 2011-7-28 01:45 PM
招聘公司:A famous IC company
0 a2 V& C( j$ ^, [- W2 y, ?3 L招聘岗位:Sr. Audio Design Engineer-DFT7 R9 I) _$ M' Y! F- @! p1 ?
工作地点:shanghai
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8 m9 w+ e; H. x! S7 r5 f: a岗位描述:4 B! _+ O% I# a- a8 J3 h: q
1.Toplevel integration and verification of IP deliveries0 z/ h0 a- e" Z2 n7 p
2.interact closely with the Audio IP team (Freiburg, Germany)9 Q7 Y3 h1 h5 }
3.Support DfT team during integration
" N- a$ t+ E9 p+ e# T4.Support Test Program Development
4 ?4 \% }# b8 A6 X# w: G5.Support frontend and backend team through the whole design flow until tapeout (in Freiburg, Germany and in Shanghai)- {# X3 j# v& O% f

% u8 O/ @* J7 i* h7 B3 S职位要求:7 h' ?  _0 t/ @
Qualifications: (Education, Experience, etc.)2 p4 R( A' H2 l$ q! O7 l' H1 V
1.Bachelors/Masters degree in Engineering (Electronic Engineering) or equivalent
2 T  {- x: b* V+ s( `2.Experience in standard EDA Tools and Methods (Design Compiler, RTL Compiler, Primetime etc.)/ l4 S% W% P" ]/ K" g5 E# K0 l5 o
3.Experience in RTL coding (Verilog) and verification& Y0 @) W1 a! ]& q+ y! f) N6 I
4.Experince with structural test (Scan, MBIST)
6 ?$ o5 y( S, g1 \" ~0 L$ Q5.Candidate must be able to work independently and interface with various groups 8 L" T& F! q5 c0 L! g1 Y
6.Spoken language: English fluent
3 ^. J! ^6 c$ f$ }7.Ability and will to travel
作者: ranica    時間: 2011-7-28 01:46 PM
招聘公司:A famous IC company
2 w8 x* Y  A0 _# `* e9 [' @  d招聘岗位:(Sr.)IC DE(DAV)6 M3 F& V" k' I& }- P
工作地点:chengdu+ W) l6 A( c# }, H2 ]9 q; ^& m  Q

& e/ y5 u: t" F+ |1 U- F岗位职责:
8 Q- o1 U6 @& s' W, c1. LSI的逻辑电路设计;
$ ^+ d* I6 d% c/ L0 t: \8 J+ R- ]2. IP整合,合成,验证和修正;# d9 w8 o3 h0 n; n
3. 综合、静态时序分析;9 c9 Y) k$ `4 w
4. FPGA平台的搭建及基于FPGA的系统验证;! R! e: u6 H& J0 z8 O/ i& e) g% w
5. 系统整体验证及调试,芯片的测试等。3 A3 A8 z' T/ n) v3 Y% Y

) {! w9 Z( |! {+ Q* D: x职位要求:. k( N* R6 s, c3 G# K; A
1. 微电子/电机/电子工程或相关专业本科、硕士及以上学历;
5 c2 |9 a/ O/ w* Z) d5 D2. 3年或7年以上IC设计工作经验,具有视频,通讯等芯片设计经验;作为Leader开发过一个项目者更佳;4 v$ x, h  T5 U, ]! }
3. 熟悉数字电路正向设计,包括Verilog-HDL硬件描述、综合、仿真等;
$ q. x' |# S2 s" N2 k3 S4. 熟悉C语言编程;( H5 |1 u' v/ _/ A! ?
5. 能熟练使用Xilinx与Altera FPGA开发工具;
( e: w1 s  q  p4 R$ g6. 熟悉逻辑综合,时序分析,Verilog仿真等IC开发环境。
作者: ranica    時間: 2011-7-28 01:48 PM
招聘公司:A famous IC company
& a# Q  t- x! j2 E' W: f3 }招聘岗位:ASIC Engineer of SOC and Video system
7 C' Q1 s( C4 e8 N工作地点:shanghai$ z/ \5 o3 q1 B$ c+ @& c

6 ^  S3 _/ h1 _0 F岗位描述:Responsibilities:9 X5 L2 W  ]. [. a' G
- SOC design% q0 _0 q' \, a2 j- u
SOC methodology define and control
- a5 S, o) L( q# gLead and audit block level synthesis and timing closure
( b/ E8 w8 |8 NTop level synthesis - x: ^3 g9 O  j* s1 n8 K9 Q
Top level STA (define SDC and be responsible to timing signoff)
. F, i' b% h: \6 t- Z* }Understand DFT flow, can do necessary support* a) E1 u3 f! r% r
- Video design3 X( P7 Y. t7 L+ A
IP level Micro-architecture, RTL Design, Verification, Synthesis and timing closure. & h7 }7 e- L  q3 O
Solid knowledge and experience on video block design and debug
+ n6 z& o! ^* \% e3 ?5 w0 s1 LTop level architecture, including clock/reset structure, address mapping, bandwidth analysis, etc
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& ^  r" B' F: i0 G# P职位要求:0 E  l8 e# h) e; I7 s) y1 O7 y
Must have:
' m+ L% H+ w2 L: BBSEE Degree or above 7 n) }/ i4 Q. T  N3 j
3 or 5 years of experience in ASIC design / {; u. M2 E2 R1 k0 I  K
Familiar with industry synthesis/STA/formal tools 4 `: m7 g8 C- a2 R/ h
Familiar with at least one of script language such as perl/tcl/shell ! ?& B( v3 i/ t' W" Q
Solid RTL design experience, better in video system
3 ~, j/ \3 ?" U: ^" e$ w8 mSelf-motivated in solving problems 7 J: F: Z" X) H' ~
Good communication skills and fluent in English.
2 h# b; ]% B9 }7 ?2 KGood team player.
作者: ranica    時間: 2011-7-28 02:02 PM
招聘公司:A famous IC company: t2 z8 R+ U+ T- I9 Z! A/ n, `; ~
招聘岗位:IC Logic Design Engineer (Video R&D)% ^, G5 C; L; B5 j" I. l" c
工作地点:Shanghai
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岗位描述Job Duties:& v/ _: b* f. ~1 J/ L: q9 Z# ?
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· IC logic design (Front End) for Video Quality Processing ICs or SOCs (System on Chip), including Video Algorihm development Verilog RTL coding, Syathesis, StatiTiming Analysis, Integration and Verification, FPGA emulation adn C/C++ Modeling.3 [/ I/ {" l3 ~/ C

/ K3 r9 d9 A0 j# V职位要求Qualifications:' }# _( {7 _0 Y2 z
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· Education: Major in EE or related, Master or above.5 Y% D- {; m  m6 Y
· Familiar with EE logic design flow, such as RTL coding, simulation and synthesis.5 i) u6 P8 T. q4 L) \* Y  G
· Can write C mode and RTL to implement algorithms.
$ |, q+ U1 ~0 z3 e2 ~! u· Working experience preferred, but not a must.5 U* |2 p2 r/ ~3 L
· Familiar with TV system and video processing algorithms is preferred, but not must.
8 P* t* b" Y7 \* U! e- g* K· Good personal characteristics as an employee good communication ability and co-work sprit
作者: ranica    時間: 2011-7-28 02:04 PM
招聘公司:A famous IC company
* i+ t. u" ^8 O% h招聘岗位:Senior IC Physical Integration Engineer
& J# E* ?- E0 B0 ~1 l工作地点:Shanghai8 f# S0 W, M  N2 [4 G
6 [) B7 F, K6 P' f# r2 a5 L
岗位描述Job Duties:
( d, c- Z- U7 d1. To execute circuit and final physical implementation related technical tasks in projects including, but not limited to IP ownership and integration, ASIC physical systems and circuit implementation, ASIC characteristics verification and validation and device interconnect verification.0 ~3 p/ e6 Q: s* D
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职位要求Qualifications:( f5 I2 `, w& a. q2 R, ~
1. Bachelor / Master degree or above.
) ^6 q# D: p! J8 z2. 5+ years experience on physical implementation and circuit design.
作者: ranica    時間: 2011-7-28 02:05 PM
招聘公司:A famous IC company
; d# [! A$ T7 W6 e- c  ?  A# P$ x招聘岗位:ASIC CAD Engineer0 x2 S; b% R5 [* N$ y9 [# ?1 t/ k
工作地点:Shanghai0 s5 z$ {. B: k" Z; G5 Z9 I

/ S' D' q) _) R  r/ |- z岗位描述Description of the Role / Responsibilities:+ S9 r' p7 @& Q& Z6 r3 k

! }4 v0 }! `' M, ~Participate in the design and implementation of the leading edge ASIC chip.$ X: P% r* h  n! J) z
Your focus is on design flow
& z' h% r- x+ ?* z0 M; YEnsure the design methodology correct and improve automation and productivity. The main flow steps include: ( `. Q# H/ x- \( [. S+ a
FE: Synthesis, Simulation, STA, Design Check and memory compiler etc.
2 D- |4 H4 O2 B8 r: ]- LBE: Place and Routing, Physical verification, Signal integrity, Power analysis etc. ; l: Z+ Q: {; z, @
Another important part of the job is doing support to FE /BE team. ) d. [' H7 z* A5 b
When they have a real design issue and can’t solved by themselves, you may be asked to jump in for debug and find a solution. Usually you will work with EDA vendors on such case. 5 b8 L# S3 @1 R, X- [- H
Responsibilities besides support project work also include interfacing with other implementation experts across different development locations, and driving the continuous improvement of advanced implementation methods to Trident digital TV and Set-Top-Box projects teams.2 {' t/ }4 g+ A

7 U' y! m, S$ M4 H职位要求Experience and Skills Required:
( V: B9 c, j$ |* x( }0 REssential" t% `3 Z5 D* h. I
Major in Electronic Engineering or Computer Science.
8 m) @+ W2 e% t" ^  R% S$ wMaster (or Bachelor 2+ years related experience)
0 H$ x6 h  }! u, s/ u  k& F+ J3 c; R; A9 nStrong programming skill with one or more following items( Perl,Tcl, C/C++ etc).
4 O0 m. M2 K9 T. z. `4 tExperience with industry standard development EDA tools and flow.
, {5 t2 E3 D' }  zFE engineer: DC, RTL Compiler, PT, Conformal LEC, NC. VCS 5 D- e$ i) v  \  D" G( k# V
BE engineer: SOC encounter, Apache Redhawk etc.
4 i1 d7 X  b% w$ s3 l& j* z* LGood written and fluent oral English.
3 z% {! X2 r; s( p5 ^5 n5 Q2 V7 Q; cGood communication skills and team work. ; `$ d% k: Y% t7 j2 \; K) c$ x
7 i5 s7 G" A$ o2 u1 o1 @2 _
Desirable0 Y3 U+ G- y4 d5 [% L, e
Real ASIC project experience as a FE or BE designer is a plus.
作者: ranica    時間: 2011-8-5 01:45 PM
招聘公司:a top 15 semiconductor company2 |! o' b/ |8 V3 u# p9 c$ L! A4 Q
招聘岗位:System Engineer
+ [! h) k9 |, ^4 w, L0 i- k工作地点:Beijing
& P& w9 c" W4 ~4 z* ]
, Z& d" A0 R" B+ s9 s& S+ R岗位描述:& Y  _+ n7 G# A6 ~
Responsibility: - Develop reference platform for image processing with XX products and third party IP/products. - Work closely with AE on demonstration system for XX customers. - Develop full functional reference platform for image processing - Deliver image processing reference platform user manual and related documentation. - Develop relationships with IP provider. - Deliver image processing reference platform training. ) L  W* K, @2 S0 ~5 |& t6 O- P
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职位要求:
4 L2 z2 s" T6 B- D2 N5 k1 f4 VRequirement: - MS in EE/CS. - 3 year+ experience for MSEE and 1 year+ for PHD. - Strong FPGA and Embedded firmware experience and skill - Strong background and experiences of system design in both hardware and software level - Strong background and experiences of image signal processing is preferred. - Strong background and experiences of PCB board design is preferred. - Good spoken and written English - Ability to work independently with multiple teams to meet complex objectives - Self motivation, good team player and good communication skills
作者: ranica    時間: 2011-8-5 01:49 PM
招聘公司:A famous IC company5 j& c# e% }5 u4 L
招聘岗位:Software Developer – SPICE Netlist Parsing( j- E1 u& C) F/ b( |0 V) B6 u
工作地点:Shanghai
- `! G# ^) Z4 j  W! N3 f/ M) u8 Y' L1 a6 T3 p1 ?
岗位描述:
1 f+ |6 M, O( m; J3 m5 ?( L7 uJob Description Develop and maintain the SPICE netlist parser for IC-Package-PCB co-analysis
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职位要求:# t5 D5 Q! [, q* {4 f6 L
Qualifications Strong knowledge of Lex&Yacc, C/C++ programming skills Experience with the algorithm and implementation of large data parsing, handling and processing Experience with SPICE simulation is a plus Good communication (written and verbal) skills in English BS, M.S. in Computer Science or other related areas
作者: ranica    時間: 2011-8-5 01:53 PM
聘公司:A famous IC company6 Z& x3 Y  k3 _9 O
招聘岗位:Software Development Engineer
) o9 H2 E; T- S9 U0 P工作地点:Shanghai6 f& x* ?) U- V9 [) q

+ q  c% `4 k  n1 x! j. N岗位描述:0 y# q+ [7 H; P, l
Responsibilities: Develop application software tools to enable Application Engineers and IC design house, foundry, OSAT customers to do test program conversion, development and optimization on V93K platforms. Develop production solutions for XX customers to improve their production efficiency. Develop conversion and other productivity tools to improve Application Engineers’ efficiency, make the tool as generic as possible and reusable. Work with cross functional teams to collect and understand internal and external customer requirements. Do solution architecture design of complex software solutions. Do software coding, following with SW development process. Contribute idea to improve the effectiveness of the SW team and Application development center.! v, k) R+ n3 a4 ^
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职位要求:
6 a4 H2 {  P- g, uQualification (Must): 1. Bachelor degree in computer science or related 2. 5+ years experience in software development 3. Excellent programming skills in Eclipse or Java 4. Strong C/C++ programming skill 5. Strong knowledge of software design & development methodologies such as , OOD & OOP, design pattern 6. Familiar with iterative development method 7. Familiar with Linux platform software development 8. Positive attitude and good communication skills, good team player 9. Strong verbal and written English skill 10. Basic knowledge on electrical engineering 11. High Passion; A quick learner under heavy pressure 12. Flexibility to travel internationally Desired: 1. Master degree 2. Knowledge in semiconductor test systems 3. Experienced in product development 4. Perl programming skill 5. Good project management skill
作者: ranica    時間: 2011-8-9 10:32 AM
招聘公司:A famous IC company/ D) K: N# d$ h" Q6 u- a. s" |  a0 O
招聘岗位:Engineer, Technical Lead Software
% U. N& `3 I8 \6 M工作地点:Shanghai# t, I, v, @6 r# ^! M# i0 s
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岗位描述:
* M  w. n! [" v2 P9 dJob Function Design and develop software and firmware for ABU SOCs. Performing customer support job functions.   B- ^7 E5 R  ?$ F
( D( U  }1 \1 r( Y
职位要求:
0 }# q/ j" n+ D9 n. M0 JSkills/Experience - 4+ years in embedded firmware development - experience in networking protocols - experience in C and Linux programming - good knowledge in RTOS Responsibilities Education Requirements - Master in EE or CS.
作者: ranica    時間: 2011-8-15 11:58 AM
招聘公司:A famous IC company* f& s+ h* \  }& O: o. u5 q* @
招聘岗位:Program Manager9 Q8 G7 Y9 Y2 q) `
工作地点:Shanghai
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岗位描述:' w/ n1 J* B' H, \# j. h. i
Job Description (tasks and responsibilities): The Program Manager will manage cross-functional teams in China and headquarters to complete the semiconductor IP and product development from concept to releasing it to production. Responsibilities will include: • Overall responsible for managing semiconductor IP and product development from concept to releasing it to production • Follow product life cycle management framework to carry out development • Form IP and product development teams including digital design, analog design, systems/validation, SW engineers and QA engineers • Complete detailed development plans including cost & ROI analysis, identify & mitigate risks, and carry out reviews • Interface with Marketing and Sales to ensure that product deliverables are identified and agreed to • Manage all the activities of IP and product development teams • Report status of the project on the weekly basis • Address customer issues related to the IP and product • Provide leadership in product development and technology competency
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/ L3 J/ S0 i& O0 h: D& N$ ]6 Q职位要求:
& W' {( R7 ~, n0 P- h6 TJob Requirements (education and experience): • 10+ years of experience designing and implementing video/image processing semiconductor IPs and products, with at least 5 years program management experience and exposure to the full development lifecycle • In-depth knowledge of video codec (MPEG2/4, H.264, AVS ) and image singal processing • Track record of having delivered complex IPs and products from concept to production • Proven experience in managing cross-functional development teams • Proven experience in developing consumer electronics products and supporting global customers • Excellent organizational, leadership, decision making, human relations and written and oral communications skills • Detail oriented and sound judgment on technical matters as well as team dynamics
作者: ranica    時間: 2011-8-15 11:59 AM
招聘公司:A famous IC company
* q+ D0 ]0 d# n' r2 P" P2 E1 M招聘岗位:Sr digital design engineer! p( `! ~7 I/ y1 h) s
工作地点:Suzhou3 T0 U  B) a% }3 A! [; q
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岗位描述:- k+ A# o. z/ X1 a; l8 L" k
岗位职责描述带领团队完成functional block划分与设计。 数字电路芯片和模块的规格制定 用Verilog语言实现电路功能,仿真并验证电路的功能 对模块进行综合,并分析时序 分析代码覆盖率
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职位要求:8 G8 Q1 O) h4 i9 ^$ @% T
任职要求基本条件 ¬--本科及以上学历,五年以上相关工作经验,有闪存控制器经验优先。 知识技能 --了解IC 设计流程; --熟悉architecture定义,能够划分合理的功能模块; --具备RTL设计经验,逻辑思维严密; --具有良好的debug能力和问题定义的能力; --ARM相关芯片的开发流程
作者: ranica    時間: 2011-8-15 12:00 PM
招聘公司:A famous IC company+ N- L; D% a* ]2 Z( P6 z1 y8 ~
招聘岗位:数字前端实现工程师" W# D" P/ z) B" n# n, P: j
工作地点:Beijing
+ g7 d$ n8 B' T# y4 ]5 b. H4 J
7 F6 W6 |- E/ l* L  V  A! m岗位描述:
# G9 M* f: y. \' f. W; F7 n1 L# |职责: 负责芯片的逻辑综合,从RTL到Netlist的实现。 参与部分DFT工作。 负责SDC检查维护,前后端设计沟通,。
8 D( k1 R3 m$ K" H7 h! l5 R, A5 j6 L2 w* d
职位要求:
% I# l2 O& r1 P) ^要求: 精通DC,PT,熟悉Verilog,SDC。 有过实际TAPEOUT经验,两年以上工作经验。 有DFT工作经验者更佳,对后端流程有一定了解。 具备团队合作精神和责任心。
作者: ranica    時間: 2011-8-15 12:00 PM
招聘公司:A famous IC company
- o7 b2 [3 m0 x+ N+ d招聘岗位:数字前端实现工程师" [2 @1 e; |& x, d
工作地点:Beijing
  {5 P8 U  ~# g2 D' w( \5 U* G( h/ g: c/ w" {
岗位描述:
8 W8 ]1 s: F. i7 A, h" W职责: 负责芯片的逻辑综合,从RTL到Netlist的实现。 参与部分DFT工作。 负责SDC检查维护,前后端设计沟通,。 : u  h% d% ^7 k2 L; b- b
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职位要求:; @8 F( r! }9 F- @# t) ]) v
要求: 精通DC,PT,熟悉Verilog,SDC。 有过实际TAPEOUT经验,两年以上工作经验。 有DFT工作经验者更佳,对后端流程有一定了解。 具备团队合作精神和责任心。
作者: ranica    時間: 2011-8-30 02:13 PM
招聘公司:A famous IC company
* n# k, u" M6 A5 H3 N招聘岗位:Senior / Staff ASIC DFT engineer (MCE ASIC)
% [- V" s2 G& w7 W% H. z% n0 T工作地点:Shanghai
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) l  C, o* u+ ]3 D( k- ?4 x8 y岗位描述:
5 x: E* q+ e- d' k  ]8 b& m; VDescription: Sr. / Staff ASIC DFT design engineer Focus on DFT design & debugging of leading-edge large SoC.
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职位要求:, k0 g! F" E1 u; X( P
Qualifications: 1. BS (MS preferred) in microelectronics, electrical engineering or equivalent with 3+ years of DFT design experience, preferably with large SoC chips. 2. Handy experience on scan, mbist, boundary scan, ATPG and analog DFT, with Mentor/Synopsys/Syntest tools and RTL/gate simulation. 3. RTL design and STA experience is a strong plus. 4. ATE tester experience is a plus. 5. Must be able to communicate in both written and spoken English 6. Good team work spirit and communication skill.
作者: ranica    時間: 2011-9-8 10:55 AM
招聘公司:A famous IC company
6 k( @+ Y* L3 [招聘岗位:Senior / Design Engineer ( Flash IP)
5 x8 y( H4 N# o  `工作地点:Shanghai
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岗位描述:. e% ]. E9 W( t3 q$ j# D3 Q. T8 z
Job Description and Responsibilities: -Design and maintain Flash memory IPs; -Support user / customer to use XX embedded flash IP. $ e+ l$ e, H' q1 ]: K+ ^% M
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职位要求:
, e% x# [0 t8 g4 n. [Key Competency Requirements: -Technical knowledge in IC design methodology; -Experience of non-volatile / flash memory, MCU analog IP design a definite advantage; -Knowledge of Verilog, Synopsys synthesis / simulation tools, HSPICE, Cadence Design Entry, IC layout tools, Dracula, Silicon Ensemble or other equivalent tools. Education and Experience Required: -Bachelor degree or above in EE; -More than 2 years of analog design experience; -Preferred:Some Analog/Layout design related experience; Some Process/Technology related experience.
作者: ranica    時間: 2011-9-8 11:00 AM
招聘公司:A famous IC company
( E3 Y0 a' g. E) q. X招聘岗位:DFT team manager (MCE ASIC)
; O1 Y& O0 O7 @3 s$ \' l" \工作地点:Shanghai2 G- B" o- ^5 H/ @/ o! ]

: j! f6 }* p/ d! T- E岗位描述:$ C' L; E; o2 n# m. g, G
Qualifications: 1. BS (MS preferred) in microelectronics, electrical engineering or equivalent with 5+ years of DFT design experience, preferably with large SoC chips. 2. Handy experience on scan, mbist, boundary scan, ATPG and analog DFT, with Mentor/Synopsys/Syntest tools and RTL/gate simulation. 3. Good communication skill in a multi-national multi-team working environment. Experience with ATE tester and Production Engineer is a strong plus. 4. RTL design and STA experience is a strong plus. 5. Fluent in both written and spoken English& Z. q1 M" R: `: x

/ x# z5 w7 j' N  l* A% x4 i% y职位要求:
+ _2 h$ T' n$ R/ k7 ]! ?* EDescription: DFT team manager Focus on leading the DFT team for DFT design & debugging of leading-edge large SoC, and work with Production Engineering team on large volume production.
作者: ranica    時間: 2011-9-22 03:23 PM
招聘公司:A famous European IC company: D: }2 n( T% n3 t" y& a0 m! t5 _
招聘岗位:Senior Digital Design Engineer, Y" o; X- ^8 L* C/ z" @# i% C
工作地点:Shanghai! u6 t. n3 ]- M7 G2 F5 A
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岗位描述:
  X" M- n" _( ]* e2 u# t- Define specifications in cooperation with international teams - Design and verify digital circuits for mixed-signal application - FPGA-based verification of digital circuits - Estimation of efforts and schedules for design projects - Close cooperation and interaction with international teams
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职位要求:( G4 u. ?: q2 j  X+ z) t! n
Requirements: - Bachelor or master degree in Electronics, Communications, - Computer Engineering or equivalent, 2+ years - Strong background in digital design and verification - Experience in working with FPGAs - Flexibility and open-mindedness; Self motivated, excellent communication skills and a real team player - English written and verbal; - Willingness to work and interact in international teams
作者: ranica    時間: 2011-10-12 10:42 AM
招聘公司:A Fabless IC design Company! T+ E1 |0 [6 l% v7 h; _
招聘岗位:SenDigital IC Design Engineer
6 ?' U' l' X  i, U5 H工作地点:Suzhou
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6 c# d; m0 [8 u5 l+ b9 Q% _岗位描述:3 W' ?9 [0 M5 v) j0 _/ e/ y
职位描述: 1、参与芯片架构设计; 2、负责数字电路的模块和微结构的设计及RTL设计; 3、进行电路仿真,协助芯片的模块级和系统级验证; 4、芯片电路综合、时间收敛、面积优化、功耗分析、形式验证、板上调试等;
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职位要求:# ?2 x) y2 e) j+ p' a( p' J3 H# ?
任职要求: 1、通信,信号信息处理,微电子等电子相关专业博士或硕士三年以上工作经验; 2、1-2年CMOS数字逻辑电路设计经验; 3、熟悉数字集成电路前端和后端设计流程,熟悉Verilog等硬件电路设计语言; 4、熟悉数字逻辑电路设计的相应EDA工具 5、有商业芯片流片经验者优先; 6、要求良好的沟通能力和团队合作精神,工作积极主动,踏实好学。
作者: ranica    時間: 2011-11-8 02:22 PM
招聘公司:a top 15 semiconductor company
6 t5 W6 p% J% F' I$ U: M招聘岗位:Digital Design Engineer3 W) X4 L- T2 L0 C' d/ Z) t! z
工作地点:Shanghai
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, U2 z  _9 _$ {* b! {; W! L/ M8 M岗位描述:
' W3 r1 k' r; V7 O- n: H$ |) pKey Responsibilities: Preparation and review of functional and design specification for ASIC (ASIC/FPGA) Prove logical functionality and ASIC/FPGA code design/implementation. Coding of digital functionality form top-level down to block level Verification and simulation of needed functionality on block level Make test plan and test strategy. Ensure effective testing and high quality product delivery. Participate in system requirement and architecture review. Generating the test bench environment for the verification Responsible for test planning, test case definition.# P1 A* A) u$ p
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职位要求:
& T0 f8 S5 u3 X" J: \& }  Q) A( tJob Requirements: SoC development & Methodology Digital (ASIC/FPGA) design experience Very good Verilog knowhow and coding and modeling experience Complete understanding of the digital (ASIC/FPGA) design flow and process. Knowledge of Signal Processing, familiar with MatlabSystem Solid background in Digital Signal Processing/Mix signal design Good knowledge on Audio/Codec Good knowledge on IIR/FIR Filter design Good knowledge on sample rate convert (interpolation/decimation) Experience 3 year + experience in digital/mix signal design.
作者: ranica    時間: 2011-11-23 04:54 PM
招聘公司:A famous IC company
- L" P. I* b, r招聘岗位:Customer Engagement Engineer (Graphics Software)
, O$ v; i! f6 t, r) W8 e工作地点:Shanghai4 a# R2 h+ a: O+ h2 k5 |0 e

$ v5 {" |) U: i岗位描述:$ @3 c1 _7 V7 p3 u( t
Background The Media Processing Division (MPD) within XX has the mission to be at the forefront of advanced multimedia IP products. The Mali range of Graphics Processors delivers an advanced architecture for hardware acceleration of graphics, tuned for low energy consumption and high performance. With considerable success to date and continuing strong customer interest we are expanding our customer support capability in the Asia Pacific region by creating a cross-functional team of software and hardware customer applications engineers. Customer Applications Engineer (Graphics Software) You will be required to gain a deep knowledge of XX’s GPU software driver products, build relationships with the relevant functional groups within XX worldwide and deploy this knowledge solving real problems in a timely manner for customers during crucial stages of their own product developments. The successful applicant will also aid in pre-sales technical support and, from time to time, will be expected to contribute to product engineering deliveries. The role involves a frequent amount of regional travel to customer sites, with onsite support duration ranging from one day to several weeks. An exceptional customer presence is essential, along with the ability to think and act remotely from central teams. Additionally, the successful applicant will be expected to spend some time each year updating their technical product knowledge at one of XX’s GPU software design centres in either Cambridge, UK; Trondheim, Norway; Lund, Sweden; Shanghai, China; or San Jose, USA.
作者: ranica    時間: 2011-11-23 04:54 PM
职位要求:
9 T1 o# a" {% v& sJob Requirements Qualifications Good university degree in Computer Science or Electronics Engineering; Post Graduate degree preferred. Other engineering or science subject graduates would be considered if they have relevant experience. Experience • Kernel and Device Driver development and deployment, ideally for Android and Windows Mobile. • Development experience in windowing systems, for example X11. • Experience of customer and sales interaction – ideally in a Technical Support, Product Deployment or Field Application role - as well as development work. • Strong software design, coding and debug skills. • Knowledge of GPU and/or CPU architecture with an excellent understanding of the interaction between software and hardware. • Experience of working in a multi-time zone and distributed team environment. Desirable • Experience of embedded operating systems, device drivers, microprocessor and embedded system hardware architectures • Knowledge of Khronos multimedia standards and Microsoft standards • Experience in 2D/3D graphics technology and standards such as OpenGL, OpenGL ES, OpenVG, Direct3D Mobile, DirectX and EGL • Knowledge of Windows and UNIX development environments • Knowledge of the XX architecture, XX assembler • Knowledge of heterogeneous compute, ideally GPGPU/OpenCL. Personal Requirements • Must be able to travel on a regular basis, and potentially for extended periods • Must have excellent written and verbal communication skills with both colleagues and customers, including good written and spoken English. • Must thrive working in high-pressure customer environments, potentially alone. • Must be proactive in obtaining engineering or management input, either XX’s or the customer’s, in order to complete tasks in a timely and accurate manner. • Must have the desire and ability to solve problems quickly. • Must be enthusiastic and well driven. • Must be able to schedule own workload and plan tasks – based on both internal and customer requirements. • Must have good inter-personal skills, and be able to work well within a multinational team; especially when under pressure. • Must be willing to be flexible and accept new challenges.
作者: ranica    時間: 2011-12-13 09:22 AM
招聘公司:a top 15 semiconductor company; H" V, k# T& w- g6 u
招聘岗位:Senior Digital Design Engineer
4 N, L. i; i) C4 w" K- Y! |工作地点:Beijing' O+ @1 I7 r, U* U% ^4 b% I
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岗位描述:
. p* n9 ]. D& @: AResponsibility: The responsibilities include but not limited to: 1. Digital micro-architecture front end design. 2. Develop RTL code for macro block and verification to guarantee functional correct. 3. Integrate RTL IPs into chip and run FPGA validation.
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职位要求:1 K. B" ?+ V7 ^# `& m, m5 r
Requirement: 1. 3+ years solid digital experience on design and verification area for MSEE/PHD or 4+ years for BSEE. 2. Familiar with scripts languages (tcl/perl/etc.) in unix/linux. 3. Good understanding on ARM processor or DDR2/DDR3 design and verification is preferred. 4. Experienced in System Verilog and advanced verification platform development (VMM/OVM/etc.) is preferred. 5. Good spoken and written English. 6. Self-motivation, result oriented, good team work and communication skills.
作者: ranica    時間: 2011-12-13 09:22 AM
招聘公司:a top 15 semiconductor company
; l% V4 ?- c! P. |, Y: Z招聘岗位:Digital Design Engineer
  X9 a1 M- A2 J! t0 w工作地点:Beijing
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岗位描述:/ [  ^; t& \* C, e4 k0 a& {
Position description An opportunity exists for an experienced digital design engineer to work on the development of precision mix-signal products for industrial, Automotive and medical applications. The candidate is expected to contribute to signal chain understanding/partition, design and verification. He/she is also expected to solve complex design and verification problems requiring large scale analyses of probabilities. % C+ h7 `# \2 Z. e# y- ~7 C/ v

( K; T5 \+ c! J- y: \职位要求:) p  ?" J; L7 ]3 l
Qualifications Basic qualifications l MS in Electrical or electrical communication or equivalent qualification l Ideally 3+ years experience on RTL related design and verification l Good idea on sampling theory and digital signal processing l Experience with ARM type cores a plus l Experience with system-verilog, systemC or another high level verification language a plus l Basic analog understanding with real mixed signal ASIC experience is a good plus but not a must. l Strong teamwork abilities and strong inter-personal skills are required l Self motivated person with a strong desire to achieve result l Good problem-solving and trouble-shooting skills l Good spoken and written English
作者: ranica    時間: 2012-2-3 04:40 PM
招聘公司:A famous IC company9 }2 k( R6 W. e' k0 ~: o5 t3 E* G
招聘岗位:Staff Wireless Communication algorithm Engineer: ]1 Z$ f5 b4 A" w1 @, n2 O6 z
工作地点:Shanghai
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& \/ j% s9 h( P' |( Q, k) h! o% r+ _4 z岗位描述:
5 D) M4 q6 D  P, a0 Y, q6 hWe are looking for engineers to design, analyze, and implement advanced wireless signal processing algorithms. Algorithms to be developed, simulated, quantitatively assessed and refined. Participate in system architecture and testing.
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职位要求:6 c% K9 A, I1 t, V7 o- k
Required Skills: Experience in receiver signal processing design for the following: Wireless PAN, Wireless LAN, Wireless WAN, and/or cellular networks Modulation and demodulation Error correction coding and decoding Channel estimation and equalization Carrier and symbol timing recovery and tracking Filtering and interpolation Experience in the following as well is beneficial but not required: Knowledge of media access control (MAC) for wireless or wired networks Smart antenna techniques such as beam-forming, MRC, space-time coding RF system design and test VLSI design DSP algorithm in ASIC Candidates should be able to analyze algorithms in terms of circuit implementation complexity and power consumption. Candidates must have M.S in Electrical Engineering or related fields with some working experiences. A Ph.D. in Electrical Engineering or related fields is highly desired.
作者: ranica    時間: 2012-2-3 04:58 PM
招聘公司:a start-up company with high performance bletooth and Wifi technology$ {$ j! n" i4 P
招聘岗位:(Senior) System/Algorithm Engineer  ]% d" ]) ?, }4 U0 A' x# A
工作地点:Shanghai
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职位要求:. @% ^* ~5 n3 F3 d! p+ ^! H  J0 X. e
Requirements: 1. Solid knowledge in communication science & technology, solid knowledge with modulation/demodulation related algorithms including GFSK, BPSK, pi/4DQPSK, 8PSK, QAM; channel decode; synchronization, timing recovery, equalization, etc. Solid knowledge of OFDM is preferred. 2. Familiar with calibration algorithms, such as AGC, AFC. 3. Proficient at matlab/simulink, can deliver fixed-point models to RTL designer, and guide the RTL implementation. RTL coding capability is preferred. 4. Debugging capability either in simulation environment or @ FPGA level & silicon level is a must. 5. Familiar with Agilent instruments such as Spectrum Analyzer/Vector Signal Analyzer, Vector Signal Generator, Logic Analyzer, etc... 6. Have more than 3 years working experience.
作者: ranica    時間: 2012-4-12 10:12 AM
標題: Design director
客户 Semiconductor China R&D Center
* F9 W; k4 Q; m8 b' f: I9 A& I地点 Beijing- U0 _* h+ Z+ s* s  Z

0 O- [+ s% N1 W/ y, e职位描述6 U' Q0 A' G- _+ |$ T8 G
Be responsible for device driver development on xx mobile SoC products and BSP driver integration in Android, Linux and WinCE operation systems.
( s: M% J% F, i' p" \Be responsible for Multimedia, Graphic HW Engine Integration on xx mobile SoC products in Android, Linux and WinCE operation systems. 9 L7 O. T/ G0 r5 \. o/ Q2 q4 H
Be responsible for mobile solution system development including functionality development, stability and performance optimization. Mobile solution means the product such as smart phone, tablet PC, GPS navigator etc.
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1 E' u% f8 z( d- n4 B职位要求
2 G: B2 G7 F8 `# r7 L* BS, MS and Ph.D Degree on EE or Computer Science with over 10 years experience.
* _# u/ V, o& M$ \2 V6 f * Good C language programming skill with embedded C programming experience preferred. 4 @' v* J* b' Y" F/ B+ e
* Good understanding of embedded H/W system based on MCU, DSP or MPU. 5 Q& i" i+ V! R! C. @
* Experience in SW development for ARM-based products on high-level OS(Linux,Android) will be a big plus. % n3 _- Y) y8 i2 r
* Assembly programming skill is nice-to-have, but not must. 6 R# B3 g" S3 A+ H1 r
* Experience with platform bring-up, multimedia subsystem, camera, 2D/3D graphics or connection peripherals is a plus 9 \  `) ]- e# d
* Good written and spoken English ability.
作者: ranica    時間: 2012-6-15 11:18 AM
招聘公司:A famous IC company" R3 K2 a% Q* [+ N; B
招聘岗位:Senior Build & Release Engineer
/ ?" E! G5 R' a; v8 p工作地点:Shanghai
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6 h6 `. m' {+ _$ n6 C岗位描述:* I7 z2 D8 d9 ~* e/ o3 p
Job Description Introduction The Media Processing Division (MPD) in xx has the mission to be at the forefront of advanced multimedia IP products for the consumer, wireless and automotive infotainment markets. MPD is also xx's center for expertise in embedded software development. Key Responsibility We are currently looking forexperienced engineers who havediverse expertise in the software industry. You will be a key contributor in many domains, including but not limited to,further developing our continuous integration, test infrastructure, and build/release systems. As an early member to this group, you will help shape the culture and direction of the group as one of the key resource to xx.
作者: ranica    時間: 2012-6-15 11:19 AM
职位要求:
  I- O5 W8 Y7 [; O8 x5 i. u$ b2 s! TJob Requirements Education & Qualifications Bachelors, Masters, or PhD (computer science or electronics engineering) with good academic records, or equivalent professional experience. Essential Skills & Experience 0 f6 S+ w+ o8 U- M' g
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• 4+ years of professional experience in developing continuous integration (or build & release)systems $ q6 g5 a9 K' n4 L  u
• Extensive software development experience with C/C++ or Java or C#
, y5 h8 B* W* g5 s3 m4 D6 K• Knowledge of Windows or Linux development environment, tools 9 g- @( k! o3 R4 T. ]
• Knowledge of software development process, Agile preferred 0 h, ^& A9 s2 D- D" E' ~
• Works well in a team environment " q1 G# b# y. U  S# |
• Excellent learning skills Desirable Skills
- Q1 H7 k9 S9 c) T• Knowledge of web-based product development and system integration- A+ [7 }2 t) g' U  E+ D
• Knowledge of version control (Git/SVN) and database management
$ n$ f3 `. F6 g* T; G2 E; i' ^ • Experience in all phases of software development cycle
6 R# ]% U( f. N. a, x0 G# y+ T • Experience in working with open-source communities • Experience in the
作者: ranica    時間: 2012-6-20 02:01 PM
招聘公司:A famous European IC company
) _! p! S) A6 F4 k招聘岗位:Sr. IC design engineer9 a  v, F$ C" E" S7 e9 p
工作地点:Shanghai
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岗位描述:7 `8 j2 ^2 t: G: V3 |% R$ k* v
Roles and Responsibilities - feasibility studies of circuits and systems (incl. HW design) - support product proposal and definition - analog IP and subsystem design and verification - top-/systemlevel verification - IC evaluation/debugging - test proposal and support transfer to production - plan and track project activities - coach junior engineers and interns 6 ^3 d# o& x( H- x' U

6 d, t( n, o- P3 C) i职位要求:! y* Z6 f- \2 S
Qualification Requirement (e.g. Education, Working Experience, Knowledge, Skills, Language, Competence, etc) - master degree in microelectronic circuits or systems - > 5ys experience in Smart Power Design - good understanding of ASIC analog and mixed signal flow (Cadence based) incl. toplevel integration/verification - strong background in smart power s/c technologies - experience in DC/DC converter and DC motor driver/control design - hands-on experience in silicon evaluation and debugging - very good communication skills, team work and high degree of flexibility - foreign languages: English, German (not a must)
作者: ranica    時間: 2013-5-17 02:36 PM
资深IC设计工程师(SOC方向)& F7 u% C! }( X! B2 J
客户 A famous IC company- O- C; E( T0 c9 P0 K: d
地点 Fuzhou
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3 V, C* ]8 e4 c( b! i/ e; \职位描述; a! e: v- \  b$ P  E' w" |5 \. J$ n
具体工作及职责:
9 j& s  ?  M% V- h1、与市场、应用等一线部门进行充分的交流,参与IC设计项目的立项、Spec定义,并确定芯片SoC架构;- V/ R( i! m! d8 G7 h
2、带领5~6人的团队完成SOC芯片项目的全流程研发、测试及量产;
6 `6 b  f+ o8 X6 ~! N3、对项目进度和质量负责,并能承担具体的技术任务;9 H. P% c5 O0 g( V5 o8 U, N7 Y
4、组织具体技术难点的讨论和攻关;
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: J0 F( b/ M; S  x职位要求5 B6 [4 i+ v3 O
工作经历及技能要求5 r2 r9 S; Q  c: \3 x
1、有至少三年以上SOC系统设计的经验和至少一年以上的团队管理经验;
- W4 T! l; Q8 [% C& c. G2、具有扎实的数字芯片设计基础,熟悉IC设计的整个流程(从设计、验证到实现);
  q7 M7 d  a- E3 {3、熟练掌握应用处理器的SOC设计方法,完成多个项目的流片;
( J) Q# w0 L/ w4、具有一定的领导力和执行力,能带领团队承担芯片项目,引导团队解决各种复杂问题;
( D5 ], u& w+ k5、具有良好的沟通能力,较强的协调能力,以及团队合作意识;+ i. d- y! v% @! x5 T6 p
6、熟悉芯片spec设计和SOC架构设计者优先考虑,尤其是基于ARM CPU的多媒体应用处理器;
作者: ranica    時間: 2013-5-17 02:37 PM
资深IC设计工程师(图形图象方向)
$ |! p, `; h/ p* t5 Y客户 A famous IC company, F! f" n1 J  L6 Q3 ?. f
地点 Fuzhou8 {% _8 R; C: G$ ?' y4 H

$ t' |. E8 E2 ]3 |& v职位描述
! t$ X# `( B4 s1 G9 ^职位工作综述:图形图象处理和视频编解码方向& a& ^/ z0 M3 p# e3 [

7 w+ y8 V5 o6 k  Z具体工作及职责:
/ N( Q. F# Z2 e( R2 E) I1、根据市场需求和芯片定位,参与并带领团队完成图形图像处理或视频编解码等复杂IP的设计、验证和交付;
( O' @$ F, G4 `" i, {6 R0 |. Q2、对项目进度和质量负责,组织具体技术难点的讨论和攻关;
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  @3 j) ?4 x& o5 C& `) l职位要求
# X# y; `4 K1 [/ }" I: D9 D2 V工作经历及技能要求
8 p1 G' N- M& g; {+ J6 Q- o3 V有至少两年以上图形图像或视频编解码等领域的ASIC设计经验; 1 c& S0 F9 V$ Q2 }+ N# y
1、具备丰富的图形图像处理或视频编解码等相关领域的系统知识
8 n9 H& c: O2 L, n  ~' v$ G6 W4 D2、具有扎实的数字芯片设计基础,熟悉IC设计的整个流程;
/ s( }8 r, i& t) Z1 i9 \" U1 k; i9 R3 p3、具有良好的沟通能力,较强的协调能力,以及团队合作意识;
1 r+ T8 z6 Y( c$ R( f6 _4、有团队管理经验者优先考虑;6 P2 n9 g; U0 L. s$ W
显示接口(LCDC),图形处理,图像后处理,视频编解码
作者: innoing123    時間: 2013-10-22 10:53 AM
数字芯片设计工程师(DFT/综合)
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8 i& T/ V: S! L: _; H: {公      司:A mobile chipset semiconductor company4 a# z; P* C. z2 o9 ]. X
工作地点:上海2 d9 Z/ j5 _) B. v  m5 f
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职位描述: $ h! u3 Z: Q) q
1、To provide and support SYN&DFT work for several projects in parallel  ( i+ e6 e# L+ P
2、Run block level implementation for each project, include synthesis, DFT and LEC 7 p! c- G+ n" U1 Q
3、Support block level physical evaluation  
' Q2 @. t1 p1 [0 ~* Q4、co-work with designer and provide block level SDC file
3 T- H' i+ Z  j3 P% D5、co-work with Back-end team for timing signoff) n% \: c9 Q3 \) F
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职位需求: 4 \& V6 y3 t6 L7 L2 |
1. 了解集成电路设计的基本流程
# ]8 e6 ~$ O' Z3 x2. 相关Synthesis, formal check 和DFT的工作经验。(3A, 3B, 3C精通一项即可)
/ F- X' L/ ?/ j% u4 R3A. 有超过2~3个项目的synthesis 经验, 用过RTL compiler且熟悉timing的相关知识  % R1 F+ J1 }3 m0 O
3B. 有超过2~3个项目的formal check经验,熟悉CPF的low power flow
/ W! a% |$ W) D) B8 F* C3 Q8 D. ?3C. 有超过2~3个项目的DFT insertion经验, 用过Mentor DFT的优先考虑 . b; ]- h4 a# O/ E9 K
3. 具有良好的英语阅读和书写能力。
作者: ranica    時間: 2014-3-7 01:11 PM
资深数字IC设计工程师(SOC方向)
0 n) x5 M0 B$ C6 n* L& n公      司:A famous IC company' A" P9 x1 E( P" t" g' N! t
工作地点:上海8 [0 J% i+ o3 @) u7 R

/ c! m: U  F5 y岗位职责: - j$ \! _/ c" k1 I+ L
1、与市场、应用等一线部门进行充分的交流,参与IC设计项目的立项、Spec定义,并确定芯片SoC架构;
$ l" V8 O) N- g: J+ _2、带领5~6人的团队完成SOC芯片项目的全流程研发、测试及量产; . X1 g1 H" X+ q: q+ d2 E, O
3、对项目进度和质量负责,并能承担具体的技术任务; 5 z, V: Y7 |* R/ C$ C
4、组织具体技术难点或紧急任务的讨论和攻关; ! V- g+ ]  F8 T, p6 z: [: k

2 z: I( _) c# I  `0 `2 o/ B岗位要求: : C# ]0 O& q& h9 A" D( |* |) e
1、硕士及以上学历,电子、通信、计算机或微电子专业;
- O( t- l7 r: W2、有至少两年以上SOC系统设计的经验和至少一年以上的团队管理经验;
: C+ q; n1 f5 Z* `3、具有扎实的数字芯片设计基础,熟悉IC设计的整个流程(从设计、验证到实现);
' }* l6 M! ^) B& e8 m0 a4、熟练掌握应用处理器的SOC设计方法,已经完成多个项目的流片; 7 {3 A" u% y. V+ Q8 K5 k
5、具有一定的领导力和执行力,能带领团队承担芯片项目,引导团队解决各种复杂问题;   ]1 s+ T# K! V3 [) _
6、具有良好的沟通能力,较强的协调能力,以及团队合作意识; # h( a9 k; ^' V- \8 h8 s
7、熟悉芯片spec设计和SOC架构设计者优先考虑,尤其是基于ARM CPU的多媒体应用处理器;
作者: ranica    時間: 2014-7-21 10:51 AM
ASIC Verification Engineer (WMAC)) |3 `% p* R% i5 ~
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公      司:A famous IC company" A* r2 e1 Z0 ]. t, L1 l6 U
工作地点:上海  B: k  V0 }3 H* ?9 q
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The Role: 6 V) x" o6 s  o1 @+ p
        ASIC design and verification . @5 L8 u7 n2 [0 G
        Work closely with the California teams ( l4 J" ^; L2 T% q1 m, p8 s
        Support chip tape out and bring up
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4 d' I4 Y1 w. g3 ^: R/ [( yRequirement:
! g8 b6 |# P3 s) N+ z+ i        8-10 yrs. experience  
& h4 C7 x' n! B$ {8 G        Knowledge of Verilog / System Verilog & Perl : e- W7 X) `8 u% C4 _
        Has worked on complex project; experience with 802.11 is preferable
) I0 z! l1 U9 H        Can work independently - want him to take over MVE
# g6 ?* b% t: i) g( A+ l) ]2 O        Experience in Networking SOC, Ethernet MAC or any other MAC layer protocol experience is plus
作者: ranica    時間: 2014-10-31 12:16 PM
Job Title igital verification Engineer
( B# W8 ^) f/ h! U9 oJob Category :Semiconductor
) ]4 l- j4 X1 U- r5 K( L& jPost Date: 07/08/2013) Y5 c0 h' t/ b% l  w9 N& ]8 U! a
Location : Singapore+ A+ ]& K# S: G2 g4 `' {8 e( ?
Job Type : Permanent9 m0 g2 Z2 B4 v7 j3 l3 K: P" R
Job Description:
& O# C! n9 q/ n4 XLooking for SoC Verification Engineers Experienced in System Verilog Tools
+ U1 u$ _  m1 R* Z8 tResponsibilities:
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Constrained-Random Verification using SystemVerilog.
$ W# S7 J* @* K1 `% WDevelop verification environment for DUT,Write and debug tests for DUT using SystemVerilog, Perl, and C.  z8 q* [/ ^1 _$ b' b- Y* c2 c
Develop Bus Functional Model(BFM) or using Verification IP(VIP) for tests/ I- A2 G2 _6 S  n( K9 s
Developing and reviewing test plans. h2 B7 u) t" U7 ~* i7 b2 s4 a
Write coverage monitors to evaluate the coverage of the DUT.
/ o, Q$ @% e  IFormal verification using SystemVerilog Assertion to verify SOC or IP is plus
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Requirements:
  l4 ]& R7 h% @7 f% n; K>4+ ethernet switch background
8 C$ @: l0 F+ o( g1 v9 X6 g8 k  {At least 3-year+ experience on digital design and verification  @; G8 G! p9 {. g
Experience on SystemVerilog/VMM/OVM/UVM (UVM is plus)
& o* X7 H* u9 o4 Q1 q$ R7 m. MFamiliarity with transaction-level verification at higher-level of abstractions is plus.
3 l6 R/ {. I( E& s+ J& L$ q) ]& AExperiences in developing measurable verification plan.
9 u. _9 |3 R/ a0 s8 ]Proficiency in UNIX scripting languages and utilities such as csh, sed, awk, and Perl.
作者: ranica    時間: 2014-11-25 09:03 AM
芯片设计工程师' @& e% U0 n0 r; n) c! f- N
公      司:A chip design company3 s" N: x/ N/ p3 P" \. P
工作地点:深圳; T* J* ^) p6 Y

7 r# h0 l. {7 X2 {/ y9 x+ G5 l$ o岗位职责:
2 u" ~2 R5 M; T" l/ H5 {     1.芯片模块的设计与验证;  3 a, B+ T% H+ K3 x
     2.独立完成模块级结构设计,RTL实现以及相关验证工作;  + K5 F$ b5 I! b" I- _0 z
     3.参与FPGA系统调试和验证;  
& x* T! F7 X! m' A( ^8 a6 W3 j& y     4.参与芯片设计整个流程。3 a' Y$ g' h) t6 ^

7 |0 _& v& h! W4 y+ X# J岗位要求: 3 ?( w8 A7 S7 W' O- Z
      1.大学及以上教育水平,电子类专业 , C0 m1 k0 z# y/ u7 a* r5 @& R
      2.熟悉数字集成电路前端设计与流程 + y8 B  q$ C) a; Z! W& J1 o
      3.有数字集成电路设计与验证经验
  [! N3 K) D0 S, Q      4.团队合作精神




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