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標題: 訊號處理及通訊系統設計技術焦點 ? [打印本頁]

作者: mister_liu    時間: 2012-4-3 10:54 AM
標題: 訊號處理及通訊系統設計技術焦點 ?
研發人員研發新產品時,常面臨研發時程和成本縮減的壓力,尤其計畫延遲和驗證的成本持續增加已變成一種慣例,而下一代智慧手機、多媒體電子終端產品、醫療植入裝置、運輸系統和車用電子安全系統不斷推陳出新,更使得產品設計愈形複雜。電子系統設計已經演變成一橫跨各項應用的跨學門領域,往往同時整合軟、硬體、數位和類比設計;此外,電子系統設計的複雜度也不再只是規模上的問題,相反地,複雜性來自於市場對規格的需求,設計與市場需求連結,才能在競爭激烈的市場中勝出。 0 n( ]+ d  q" h3 J, |9 ^
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為了因應推陳出新的複雜設計,研發團隊確實需要新的工具和方法,才能整合各領域專業,並掌握從系統設計、模擬、實現到驗證的黃金開發流程。為協助研發工程師們解決上述挑戰,全球工程研發大廠MathWorks®與鈦思科技,將於4月24日與25日分別在新竹、台北舉辦「2012 MATLAB & Simulink訊號處理及通訊系統設計」技術研討會,會中特別邀請MathWorks資深工程專家Giorgia Zucchelli博士,提供從設計、模擬、實現到驗證的無縫開發技術及改善方法,並發表MATLAB and Simulink 最新版本-R2012a,介紹本版本最大特色:由MATLAB自動產生HDL程式碼,並進行FPGA-in-the-loop驗證及加速設計;以及最新射頻、類比/混合訊號的建模方式,並示範最新加速MATLAB至C及至HDL的方式,協助您建立最佳黃金研發流程。
作者: mister_liu    時間: 2012-4-3 10:55 AM
新竹場
) I; U/ N: f2 ]" R6 J; `) M2012年4月24日(二) 8:30~15:407 H0 w- A: k, h6 O0 T5 R
新竹科技生活館 集思會議中心愛因斯坦廳
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/ x/ [  A7 n8 I" ]: k) M3 x台北場 ! ~8 d9 }; G0 M" s2 s
2012年4月25日(三) 8:30~15:40
( _& S) G' \$ F: ?% Y集思台大會議中心蘇格拉底廳
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. |) i5 W8 z# T3 W% X' K# H, fWhy MATLAB & Simulink?
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; f0 K8 Q" l, r. }3 `MATLAB® & Simulink®目前已被全球工程研發及科學研究領域的工程人員所廣泛使用,應用領域包括高科技半導體、電子、通訊、自動控制、汽車電子、新能源開發、財務模型開發及科學研究等。根據全球超過100萬使用者的經驗,使用MATLAB® & Simulink®開發工具可以降低75-90%驗證時間,以及縮短50%的產品開發時間,工程師在設計單晶片系統、類比系統、混合信號系統及其它複雜設備時,可以在單一設計環境中,使用控制邏輯、狀態機以及類比和數位元件進行不同精確度的建模,整合類比和數位設計工具開發的模型也可以直接轉碼成C/C++ 或 VHDL®/Verilog®程式碼連結至外部硬體進行實現及驗證。
作者: jcase    時間: 2012-4-16 01:49 PM
適合對象
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9 w# E0 ^, ^8 g. h2 b8 p主辦單位
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作者: jcase    時間: 2012-4-16 01:50 PM
時間題目講師
AM8:30~9:15報到
AM9:15~9:25歡迎致辭
" r% t3 G5 Z. }Jinny Lin
& r( Y$ ?& F1 NTeraSoft
AM9:25~9:55MATLAB & Simulink R2012a 新版本發表Jerry Tung) `  z( z. A% @' b' i
TeraSoft
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AM9:55~10:55
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射頻(RF)系統和相位陣列(Phased Array) 訊號處理系統的建模與模擬 < 內容簡介 >
0 N) b" z) A5 _/ z2 _- 射頻(RF)系統的建模 ( Z; r# |6 U( l
- 相位陣列(Phased Array)系統的建模
Dr. Giorgia Zucchelli
7 I8 O& {( {$ X- f/ T: yMathWorks

( n! Q6 d3 M' B/ U! C5 w$ R* eAM10:55~11:15

" O, \' ]3 @2 l' J休息時間

2 ~6 @0 u& n) l0 l3 NAM11:15~12:00
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複雜類比 / 混合訊號的建模與模擬 < 內容簡介 >
; s9 T2 c4 J9 T, X: M7 I- 類比數位轉換器 (Analog to Digital Convertor, ADC) 的設計
1 ~6 K1 `, D. ^1 [; G% e- 交換式電源供應器 (Switching Mode Power Supplies , SMPS) 設計
Dr. Giorgia Zucchelli+ T$ I; r9 E9 y
MathWorks
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PM12:00~1:00

/ }6 i9 D! I; N: D" w2 o! j1 k3 O午餐時間

& O$ ^. m0 Y: NPM1:00~2:30
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加速 MATLAB 程式碼執行速度-以訊號處理和通訊系統為例
% Q, ~6 ^& n2 T; R) z3 O- @- 利用MEX程式碼自動產生
: k5 m8 a3 X0 s3 A( Q0 n6 z! I- 利用多核心加速7 z, H4 a& H  n. j
- 利用GPUs加速
Dr. Giorgia Zucchelli
2 k* V+ X: S+ MMathWorks

2 W7 o8 b/ h& oPM2:30~2:50

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% ?: |" F% V, q, ^( g8 SPM2:50~3:50
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FPGA 迴圈 (FPGA in-the-loop) 驗證和利用 HDL Coder 加速 FPGA 設計
Dr. Giorgia Zucchelli
# j% H( z/ m, T" YMathWorks

' B/ @0 i9 K+ CPM3:50~4:00

8 y- s+ m! B/ e% A( Z問題討論

7 h2 ~  Y0 R4 q; ]; h: g講師介紹

" O- w6 v; N, U% y' {% ^' c& v' PDr. Giorgia Zucchelli
Giorgia Zucchelli 目前擔任 MathWorks 應用工程師一職,主要負責訊號處理和通訊系統設計,於 2009 年二月加入 MathWorks 之前,曾在思智浦半導體, (NXP Semiconductors )工作近6年,主要負責 RF 的設計和驗證及混合訊號系統,提供建模和模擬之技術。 Giorgia 擅長利用不同運算模型進行建模及模擬,以及自動產生程式碼。攻讀博士期間,曾在微波頻率下,開發砷化鎵 (GaAs) 裝置之黑盒子模型。Giorgia 擁有義大利波隆那大學電子通訊博士學位。

作者: globe0968    時間: 2012-6-25 01:58 PM
標題: 六足機器人移動matlab外包專案(急件)
【專案詳細】% n8 d: n( j, H  t2 B& _& {( ?
1.工作內容:我們需發包仿生六足機器人移動的MatLab程式
( ?! B6 i$ \9 c! h- ~2 k3 ^2.配合時間:6/22~7/31
, C, t8 F$ {$ U# W3.配合地點:z發包後可在家作業7 O/ E4 {( }8 V: J8 l7 x  w- {
4.專案預算:20K~50K# b  U) j6 d: \# {0 |9 N) T
5.注意事項:需要對機器人的動態有認識與瞭解  , C9 z5 {- ^) v; \
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【所需專長】
/ `2 X: i, V3 E6 S4 f9 |! J稍微了解機器人的動態方程式
' b/ u- _- `- Y# o" u對matlab熟悉者7 F; H- A! I3 x* R: K( y  Z1 O
手邊已經有相關的C語言
1 u  h4 J  ]3 B6 ]9 Y可以的話,把C++轉換成MatLab即可
作者: jcase    時間: 2012-6-25 02:04 PM
標題: 編寫研究所學期報告外包專案
【專案詳細】 ! p$ b* z8 ]0 \7 l, A% b

9 n" E* F' r% A; E3 i6 c1 [7 O" k1.工作內容:我們需發包編寫研究所學期報告,接案方需熟MATLAB, 因報告需用MATLAB設計,略懂微積分,報告形式跟論文相似,唯字數4000字以上即可,相關資料, 提案方本人會提供, 若可以可先約在外面討論
: q* b1 G. G: Y7 C, c9 `" e$ ^2.配合時間:要視專案情況而定,需6/20前完成,在學學生或上班族不拘,全省皆可
+ l1 q6 F8 n3 a7 M; z! G) R3.配合地點:發包後可在家作業/ t+ I' x" g; m; T) v) ]" a5 T
4.專案預算:詳談報價. N0 g0 }0 q+ S0 U  f+ a
5.注意事項:意者請先來信附上相關作品及簡歷  ! ~6 T4 T& B' r1 B
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【所需專長】 1.熟MATLAB
作者: mister_liu    時間: 2012-11-27 03:00 PM
標題: 電子系統設計的流程自動化
每當研發時程和成本縮減時,電子系統研發人員往往必須面臨研發新產品的壓力;這雖然看似是一場艱難的戰役,尤其是計畫延宕及驗證成本持續的增加已變成慣例,但仍有一些研發工程團隊不僅能讓他們的計畫時程和成本在掌控中,並且能為他們的設計創造新的元素。( I) {* R6 Y- w6 f; j% H
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研發人員已充份認知電子系統設計的複雜度不再僅是規模上的問題。相反地,此複雜性是源自於對規格的需求,並能即時與現實市場上的需求連結在一起。電子系統設計已成為跨學門領域,橫跨各項應用及領域,同時整合軟體、數位和類比設計。這些團隊認知到他們需要額外的工具和方法,才能讓工程師整合自己專業領域外的知識,以解決新的複雜設計。
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解決逐漸增加複雜度的方法之一,就是將特定的設計任務提升至抽象層級,例如硬體驗證與整合。此由下而上的解決方法進而發展出以C語言為基礎的電子系統層級(ESL)工具,不過由於今日的電子系統層級(ESL)工具並未能有效彌補其與基本工作流程的缺口,以至於工程師仍舊飽受複雜的系統設計之困擾煎熬。1 G5 K/ j2 p$ e* p3 n2 q8 N
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追根究底,這些缺口來自於一個簡單的統計資料:產生計畫延宕且高額驗證成本的最大主因是太晚才發現研發過程中的規格錯誤。典型的規格無法滿足系統的需求,以致於工程師無法有效評估設計方案並有系統地來測試設計。結果,過多的成本和工程師的時間都耗費在錯誤的規格上,而不是用於創新和創造IP。' q! V6 G7 `) k6 d

' i" M7 [2 P/ Q所以,目前已經有愈來愈多的公司逐漸地傾向使用模型化基礎設計(Model-Based Design)來解決上述問題。透過模型化基礎設計,他們可以將現有使用之演算法開發和系統模擬的工具以及後端實現設計的工具連結起來,進而創造一個工作流程,橋接不同的開發設計領域,使工作流程上的設計缺陷能提早被修正,因而降低驗證時間,最後提高創新比率。
作者: mister_liu    時間: 2012-11-27 03:00 PM
抽象化的系統模型通常以圖型化表示,並以高階textual語法呈現,諸如MATLAB,已被廣泛使用來進行快速概念探討及演算法開發。透過模型化基礎設計,該系統模型可在真正投入硬體原型化或軟體實現之前,用來驗證設計概念的可行性。隨後,此模型在整個開發過程中扮演多重角色,包括做為可執行規格之參考(reference)、做為整合與驗證之虛擬環境、可產生嵌入式C程式碼(Embedded C code)並與RTL整合。: Q0 m/ Q' M, N. ]
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在以C為基礎的設計方法中,模型化基礎設計有兩種不同應用可展現其優勢。首先,從MATLAB程式自動產生程式碼,可取代傳統定點設計和手寫C程式碼的工作。其次,其多領域(multi-domain)之模型能讓系統架構進行高速模擬,如混合訊號設計,及訊號交互作用演算法分析、數位硬體和類比電路。在上述兩個範例中,演算法開發者和系統架構者可以描述設計決策對系統行為之影響、進行更快速之反覆設計(iterate design)、並進而在早期階段找出整合問題及確認設計流程。8 L9 H+ S& d, ^6 j( c5 X
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為了維持驗證工作流程之連續性,目前在模型化基礎設計環境中,MATLAB和Simulink系統層級模型與演算法,已可和許多EDA供應商之數位與類比硬體模擬器,以及一些市面常見之嵌入式軟體IDEs與即時操作系統(real-time operating systems)可互相連結。這些介面亦均支援協同模擬(co-simulation)及程式碼自動產生流程之自動化。' P: e; r: j0 `! K1 `. P! Z1 o
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現今有一些迫切的系統層級問題難以用傳統的軟體和EDA來處理。不同於C基礎的電子系統層級(ESL)工具,模型化基礎設計(Model-Based Design)解決的方式,是提供一系列連接從概念產生到實現過程,以及自動產生程式碼之工具,讓工程師能解決複雜的設計問題,高速混合訊號設計的最佳化即是一個例子。
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2 f6 H+ L6 {' ^/ z" G# C6 j. O( J2 pMATLAB及Simulink因能與許多EDA與嵌入式開發工具連結,其所提供的模型化基礎設計(Model-Based Design),優勢在於創造了一個統一的工作流程,有助於緩和不同工具與工作流程間的差距。 (本文由鈦思科技提供)
作者: ranica    時間: 2014-7-31 12:27 PM
工艺工程师" q3 F- l, |9 C' }5 t
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公      司:A famous IC company+ w% p  n0 D2 q2 d5 K
工作地点:北京6 @+ n; P3 D8 s; T8 G  ]
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岗位职责  2 ~+ Q- ^6 r2 `* e
1、执行公司已认定的制造工艺流程、工艺参数及产品标准;  # ^- M: U3 a' W. Q0 Z# o
2、执行工艺流程、工艺参数及产品标准;  
9 g$ H% R9 n: I( w3 Q8 H" q+ n3、优化工艺流程,解决生产现场存在的工艺、技术问题;  4 i3 x2 J( ?9 ]  \
4、检查各工序的工艺执行并做好记录,对现有生产技术进行必要的研究并提出改进建议;  2 X5 i( u+ M: b5 `6 @
5、负责完成产品的试产报告与工艺分析报告。  9 `% W5 L/ F, G- k) S# H
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任职资格  % [; f8 q) c" ]' I
1、微电子、半导体材料、材料物理与化学、等离子体方向本科及以上学历;  
+ c; Z, G: F! r' c2、3年以上工艺技术工作经验,熟悉光刻工艺、刻蚀工艺、MOCVD工艺者优先考虑;  / s) w& f6 C, w3 m$ ~+ l
3、熟悉生产工艺、产品性能、产品结构,具有丰富的项目开展经验,团队意识强;  
8 x& W$ x* E$ D$ v4、能够阅读并解释、运用各类技术文件及说明,具备解决现场故障的能力,统计调查分析能力,善于发现、寻找并解决问题;  
1 i- {' g! s9 A3 c7 u5、有责任心,能吃苦耐劳。
作者: ranica    時間: 2014-7-31 12:27 PM
CIP Engineer1 l; d' ~* v9 p+ b( \& r6 \

9 U# S; f2 }% R7 `# S公      司:A major supplier of wafer fabrication equipment and services to the worldwide semiconductor industry
# @7 j, C! M+ g3 l% i# H0 k工作地点:上海
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Overall responsible: 7 \% W3 @0 T8 r" T8 d
Responsible for delivering CIP solutions and proactive productivity solutions.
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1 i" P' o- e9 p2 sResponsibilities and Scope:
' O) ~5 f5 B# F9 t+ G-Gathers, validates, analyzes, and communicates equipment performance for assigned installed base.
0 ?0 t, Y9 ]9 J, U. j9 ]! T-Identifies and communicates revenue opportunities & product improvement opportunities.
, f/ I. D4 C! u9 B. ]2 G$ }1 f  _-Closely work with Account Team and customer to ensure on time delivery of CIP and productivity results.
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* m, ^7 a; r3 a8 C0 R8 eCompetencies:
; s5 R; m  g8 t& E, o-High level of system technical expertise. 8 u4 o  A2 A$ w& o9 {! H; P
-Excellent analytical skills.
% q. {5 J. u- h2 f; H-Excellent technical presentation skills.
" Q- Q7 r2 L) _9 q-Strong ability to influence in a cross-functional environment.
$ c# H$ }4 r3 M: Z. X-Excellent understanding and ability to apply SEMI Standards to equipment performance data. & }  g7 R7 k# S% N) r7 t
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Requirements: 3 j6 J6 o7 o6 _5 M& a: e
-BS Degree (or higher). ( S- ]" j' r" I5 u0 I) I# E
-Minimum 7 years experience preferably on Lam equipment. 9 O) O5 q. J+ G3 [- _. q  `: d: L
-Expert level process or service experience.   P$ C' Y. s) E2 V
-Strong understanding of Semiconductor Fab Operation.
作者: ranica    時間: 2014-7-31 12:28 PM
ield Service Engineer (Etch)
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: h& x% y/ A7 o. D3 x7 f公      司:A major supplier of wafer fabrication equipment and services to the worldwide semiconductor industry
! |6 K. l+ C; v工作地点:西安
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" d; A6 K2 K3 N, ]' y0 e1 VResponsibilities:  + _8 l; M6 U2 a! e, ^/ H
-Be responsible for quality machine installation and maintenance service of complex electro-mechanical systems.  ! v4 y1 a  J/ E9 v6 B) D
-Analyze and troubleshoot technical problems.  
6 a/ _0 M9 w( x-Draft technical reports.  
. a' g4 I) o1 ^: }. [9 H; b. \-Extend interface with Lam customers and provide training to customers.  , D/ L8 g) t; y
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Requirements:  : ~4 g& O( a' Q/ i. {
·Bachelor degree, majoring in Electronic Engineering, Mechanical Engineering, Semiconductor Engineer and etc. & H) L; S# u0 _6 G
·More than 2 year relevant working experience.  6 s" r7 R" u5 G2 d9 `) W
·Effective communication and interpersonal skills.  
8 C4 C' c$ g* h5 t9 b·Good team player, willing to assume hard work.  & H* A- `* N5 K0 G, L
·Fluency in writing and oral English.  
3 O- c- ]' y( l* s: `5 t·Overseas training will be provided.
作者: ranica    時間: 2014-7-31 12:29 PM
Device development engineer
; A  J1 c0 ~* a# ^1 f! W
( k1 B2 N# `) j1 P) |公      司:A famous IC company7 F& `$ W" Y3 W# {  l7 F6 |
工作地点:上海
" r) r; J  L9 S$ c  P/ f! B* ]- @* m" J: A1 f6 i+ J
Duties ( Q6 x) Z+ z0 z+ w
·         Facilitate product design work in foundry process(LG, MS and BCD process).   " J. q+ X- Y/ s7 v# Y
·         Have a strong device/process background for 90nm~0.18um logic process, mixed-signal, embedded FLASH memory, and BCD process. ; Q- a. a* G( a5 a1 c: C) `
·         Tasks would include answering device  and process related questions, interpreting DRC and LVS results, helping with tapeout and mask ordering, doing jobview mask inspections, and also participate the process/device development projects.
$ d" g- c2 V" f·         Would be expected to establish relationships with his technical peers at foundries and discuss important technical issues with them on an almost daily basis.    ~& b4 K0 A( {- f6 h
9 o( b+ U  i. V# F
Requirements
6 `9 g7 A' O" Z+ g( g·         Senior level engineer (minimum 8 years experience with BSEE or minimum 5 years experience with MSEE or PhD) . m" J- |" m: l% S! j
·         Excellent device knowledge (LV CMOS, BJT, BCD, embedded FLASH memory, OTP/MTP, latchup, ESD, device reliability)
5 T& W$ D8 j: I) w7 U0 o·         Excellent to very good knowledge of PDK systems (design rule, verification software, mask ordering, device pcells, circuit modeling, parasitic parameter extraction, and so on)
. i5 x% G2 a9 W·         Some knowledge of circuit design, primarily from a device usage standpoint.  2 ~% Q5 J# c2 p. j6 f
·         Knowledge of major Asian foundry systems, process technologies, and devices would be a positive.  " E7 D0 o, A$ w1 X  g5 @, l
·         Ability to understand and solved technical problems relating to semiconductor devices with a minimal amount of guidance.
" v+ W( Y, g4 {- E+ Z; U·         Excellent people/communication skills
作者: mister_liu    時間: 2014-8-5 02:51 PM
模拟电路高级工程师
+ z: S. F9 s: K/ p6 ]
3 J1 y* [) k* Z* @公      司:A Chinese integrated solution supplier6 w8 c6 L% j, x1 b3 V. H7 ]( `3 H
工作地点:深圳
4 I+ D, C: e& t( G1 w( i0 {
: E" L6 m* u, `4 ]& K- j岗位职责: % _! v2 W* @8 X1 @
1. 微弱信号检测电路研究;
; ^5 _  n% z5 @& M/ |' h2. 芯片方案原型平台设计与调试; ) I3 Z9 |  H& N; y

6 E. {7 A- i; \" {$ \8 e任职要求: - J/ v, J- P8 q1 D( {* N8 _
1. 本科及以上学历,2年以上相关工作经验;
5 x, N) c+ g; l2. 通讯、电子、自动化、物理或数学专业;
$ G4 o+ Q# ^- h6 B, M% z3. 思维灵活,有创新精神;
作者: mister_liu    時間: 2014-8-5 02:52 PM
AET AE
/ N9 S7 e* Y4 ~2 O& j# i7 _0 f+ A4 L& }  k9 P% A3 I' I
公      司:a world leader in graphite material science- p1 J+ V7 s# @' k& n0 |
工作地点:上海" q( C. r6 @: X3 l+ ?  p

2 e5 t+ ^+ o/ m2 f职位描述' h8 x+ O8 o4 `0 D' J
Works hand-in-hand with customers, the Sales team, and our converting partners to present our solutions and provide in depth technical assistance on our products and customer designs/applications as appropriate7 C, f3 C7 W! l. X* V
Works with Marketing and Sales groups to review product and technology sales tools
1 I8 g* m8 R0 I8 Q% l+ Y1 c Provide insight to NAD, R&D and Marketing as to what products customers need now and in the future  
- X  a/ w6 Z0 y- P1 b Attends and presents technical papers at trade shows and technical conferences as needed ; w3 q# ]4 f# o1 o2 W+ t
Interacts and supports R&D when required, especially on NAD projects that are near to market; writes reports (internal and external) detailing experimental work and conclusions1 s$ `  l& q: v# y7 b+ f; \
Keeps abreast of developments in the thermal management arena as well as the markets that could most benefit from the use of NG抯 products  
. S0 ^; e- X4 ?. C; O! N Participates in teardowns and thermal analysis of complex electronic components
# O' X/ B1 ]+ X) c4 n; A7 A6 a, y3 f Works with CFD modeler to establish mechanism of thermal problem and identify potential solutions   p# L. Q# z6 F0 ]. @$ `
Maintains a strong working knowledge of NG抯 product offering and communicates the strengths and weaknesses
% c) T2 i6 u9 {; w% o Maintains a strong working knowledge of our converting partners and NG抯 manufacturing processes and supports these teams as required during production activities
. J0 f/ L3 D) H0 ^6 ?2 N9 V8 `7 E Plans work using Microsoft Project and Prochain tools for the appropriate projects  & c/ N, O, {  J: ?" _
Uses Lean Tools such as Kaizen, VoC, and Product Concept Statements in their analysis - B+ @7 m8 c/ l& U, G
Writes idea records and reviews/contributes to patent applications; helps to enforce our IP strategy
作者: mister_liu    時間: 2014-8-5 02:52 PM
职位要求
8 L7 a1 o) z. z5 QKnowledge / Skills / Experience:
' s4 N( h! V& u; H& K8 v, b Degree required in scientific/engineering discipline: 1 t+ x7 Z- l: e- R2 ?  ^& c
5 years minimum experience for Master抯, or ; U0 P7 B; C6 q0 p7 d- t* k* L
10 years minimum experience for Bachelor抯.
5 N0 W% D9 y0 [5 m5 q) y% H3 N Knowledge of fundamentals of mechanical design. ! L" k% W1 O3 v& c% w& B
Strategic selling.
  ^+ g& O8 w# F4 X- E; W0 w) Y; @ Training or ability in project management. ) S  s# b: h- b3 L  F7 ~
Proficiency in word processing, spreadsheet, and presentation software.   O8 |- \" O- g& Q
Strong hands-on ability in handling complex electronic equipment. 4 @  b6 L; r9 [, d& l& x
Verbal and written communication skills needed to present complex technical information. 1 J7 C9 \' G4 F
+ y. h8 U& b1 e$ H! g0 w
Special Skills: 8 P0 L6 W! @' A0 V) D" I
Working knowledge of AutoCad, Solidworks / \3 [* L( Q- _6 y
CFD and FEA analysis a plus but not required
- i! M2 i7 I. A$ ^: e Fluency in Japanese or Chinese required
# Z/ v2 ?( |9 C4 Y Position is located in APA region 1 o" \7 I2 P  f8 \
Experience required in one or more of the following industrial areas: Notebook/netbook computer, advanced LCD or OLED display technology, design, or production, or lithium-ion battery/supercapacitor technology, materials, or design
: d3 \" J/ g# m: D
5 g0 j8 B+ z" cWorking Conditions:
, @$ Y( u: I) \4 @8 [0 J/ j Domestic and International Travel ?up to 75% ' b8 N9 _/ Z2 }3 H. U/ B
Work is typically performed in a home office.
作者: ranica    時間: 2014-8-7 10:55 AM
Sr Analog Designer: \! @" ?+ p, d5 O
3 C: f2 t4 u1 Q) c! H, H
公      司:A leader in high performance analog and mixed-signal IC design
, P! c; B  R9 V6 \% ?工作地点:北京. n/ I, e4 C, n! F# Z- c/ t

7 N; L7 E8 O6 [/ e6 D$ ~% h0 Z" e' {职位要求1 s% X! l: ]3 g* k  q  Q
Education and experience requirement 5 ?) u" J; P; V% b. Z
      PhD in EE, MSEE and 5+ years of and/or mixed-signal IC industry design experience; or BS and 6+  years of analog and/or mixed-signal IC industry
- T5 U  J- V& L! [2 ?2 u. kdesign experience
5 l0 A4 O& Z  ?4 F      Hands-on CMOS product design experience in two or more of the following
9 q5 s/ _2 W$ Z6 p7 iareas ) w4 i3 Y& E/ F4 m
       Receiver front end, including analog front-end, demodulation, channel selection etc. ; w( @7 X- |, E0 W" x% u7 P
       High-precision ADC, including sigma-delta, pipeline etc
, M, L( v5 |: Z' M/ D6 Q       High-precision DAC
8 B/ o' H# v8 J; W7 A6 S2 W       Fully-differential continuous and discrete-time (e.g. switched capacitor)  amplifier/filter design
( n" Q  _: V. H" l# N2 p, q, e       High-precision oscillator/PLL/DLL 4 _$ l- G9 l" |9 y9 N6 h
       Low noise voltage reference 3 f# o7 ?3 r9 V" |; e
       On-chip high-voltage charge pump 0 ?  T( Y  v) Q% t, X5 k
      Experience in system level definition, modeling and verification a plus # W2 h- v4 O4 S' }6 s( t' L
      Hands-on experience supervising layout and post-layout verification " \! v& m: ~6 p* P
      Proficiency in tools
' [+ n; W. J2 p) \1 s8 Y       Cadence design environment
6 j0 K! R7 E! ~* R" X       Verilog/VerilogA/Matlab or other tools for system level modeling and verification  a plus
作者: ranica    時間: 2014-8-7 10:56 AM
高级研发项目经理: E- N3 O" ?3 V  T$ r4 H
: Q5 u5 P) f' S( O3 R' E. @( P, H" y
公      司:A mobile chipset semiconductor company' A; X. u3 d7 z! M
工作地点:上海- `* {2 n. `0 f+ \4 V

" Z2 H7 z! S+ k/ N9 m职位描述
: ~* H- V2 ^/ m  D5 I需求说明:全面负责公司产品的研发项目管理,包含前期产品定义、可行性分析,立项后芯片、硬件和软件研发,最终推广客户并实现交付客户满意产品解决方案。  & D+ W/ k& b2 o  K/ \9 N5 ~! X
9 z; a$ I0 ?% ^
招聘需求:  1 a2 K3 F8 A* a  D4 I  j
1. 半导体、通信、计算机软件或电子类相关专业本科及以上毕业。
7 g( _: ?- F  A0 s$ W. n# k2. 有5~8年的半导体、通信行业芯片或软硬件研发经验,1~3年项目管理经验。 3 n* p8 T3 E7 H: P
3. 熟悉移动电话架构,特别是芯片和软件架构。 2 ?! w8 m. r: k6 [9 ^, w7 ^5 @
4. 了解移动电话开发生命周期,包括规划、研发以及市场推广。 / [0 D" |/ \* T7 U  j2 }
5. 良好的沟通能力,特别是跨部门沟通能力,系统和结构化的思维方法。 & y5 D$ h; x) D  ~: v" `
6. 具有较好的英文听、说、写能力。 3 K! T; B: ]; b% b3 f" C
7. 有海外工作经验者优先。
作者: ranica    時間: 2014-8-7 10:57 AM
LTE DSP RF驱动工程师
8 e, R/ W% D* `, X0 Q  S1 ^9 c- t* R6 l0 f- z! c4 w
公      司:A mobile chipset semiconductor company& d! _# {9 q- W* G( A
工作地点:上海3 T9 y0 v) ?/ n- c

4 V6 A5 `" f  U4 f+ C7 H职位描述5 k) x' q+ C( X, f1 Z7 }0 A( [5 H
1 通信工程/电子工程等相关专业硕士以上学历,3年以上相关工作经验  
8 F5 n7 k. |* g% q% x- i2 熟悉无线相关RF(如:MAXIM射频芯片)调试流程,熟悉LTE射频经验优先.  * h# W( x2 h# G2 A, A
3 有半导体及芯片公司基带+射频模块调试经验者优先.  
: T7 U* h( H" J7 S# A4 熟练使用仪器仪表(示波器/逻辑分析仪/频谱仪等)调试硬件问题  & C6 I( F% _" `+ s
5 熟悉C语言,具有基于DSP的C编程与调试经验;  
* Y$ m1 s& A6 s- o6 对工作有激情,勤奋、踏实;可以很好的进行团队合作;
作者: ranica    時間: 2014-8-8 11:38 AM
Principal/Senior Engineer of Analog PHY or SerDes IC Design
) E' P6 W+ u+ B1 m2 T, k2 T0 r5 w7 R9 V5 X  C9 `$ ]
公      司:Semiconductor China R&D Center
6 T8 k! v7 I3 F5 u工作地点:上海% t5 ^, Y9 a0 s; {' g
, H6 F% |2 b6 f4 S$ H" r; h
Job Description: * W5 @. V; ~0 i1 J8 {/ G. g, H
  q1 A  `7 n. j/ W. _, K
1.Responsible for the design and development of PHY or SerDes analog/mixed signal IC circuit blocks from initial concept and specification through final verification and conformance to customer requirements.
% b0 b" d7 z* ~) E; a. ]- D4 t+ p# ^
2.Candidate’s background should demonstrate good problem solving skills, excellent analog aptitude, good communication skills, and ability to work cooperatively in a team environment.  
! ~, D% R8 Q. [# q, C$ E- U& k+ j& p! O" ^! L$ B  G* {3 ?9 Z& F5 J! a- p7 U0 P
3.Must have demonstrated experience in analog PHY or SerDes transceiver designs including some of the following circuit blocks: System level modeling by matlab, C, or VerilogA; Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; Bias and Bandgap; Voltage Regulators. / v) G* T+ l1 h

/ N+ K5 ?6 O4 |$ I. P* d4.Candidate should have working knowledge of a set of common SerDes standards and their electrical requirements, and a thorough understanding of jitter.
$ B7 ~+ Q# h* A
+ H1 ^& {$ ?1 u5.Position requires proficiency in using CAD tools for circuit simulation, layout, and physical verification (Cadence tool experience, lab test experience, and experience at 40nm and below technologies are a plus).
作者: ranica    時間: 2014-8-8 11:38 AM
Position Requirements:  
) w3 X% p" Q$ U, x' B+ g; }
, c' k5 U: b6 Z5 L: m) O) V⒀ Master qualifed industry experience for at least 10 years & performed core role in this field.
% `5 V& Z. g/ q& E2 C9 _/ R" h( g; R  f
1.Master or PHD (prefer) degree, major in Micro-Electronics, Electronic Engineering or equivalent 0 z3 x% K$ n+ h2 ~6 {
- P5 s8 N( e- d% v6 \5 S) g6 a
2.Ability to work effectively alone or as well as in a team. % o% C, ]* o$ y# s2 O1 e0 F, Q

7 u8 n1 M" o0 U+ S/ X3.Essential that the individual demonstrates strong communication, verbal and written
: Y  B* z4 _: g7 W
3 i) U  w( \; T4.Requires good communication skills in English.   n+ V3 K4 t0 l5 x3 U8 @2 b- [

! A/ G& K: g' M2 I* {5.Industry Experience for at least 8 years or more for analogy PHY or SerDes and High Speed silicon mass products6 O! T' ?! M3 k9 ?

! D$ T0 p+ j" m( F8 K% M9 P: ^" P+ uDesirable Qualifications: * X: V" c$ x- Z9 y* n  c# @8 t- ~
2 M1 T. S$ D; H/ ^2 a, O4 p8 V- }
⒀ Analog PHY means both SerDes(for connecting one-connect) & HDMI PHY, DP (Display port) PHY solutions. - @9 Q7 ^6 P/ f2 L

9 x3 Z% `2 j& M, `1.Knowledge of one of key SerDes Analog IC design areas and their architectures/applications: $ g5 ~4 C6 _) W) G5 S1 _) T, d6 ^
2 U0 R+ V: `! _  s* v4 Z0 Z+ {
2.Clock Data Recovery; PLL''s; Oscillators; Low Noise Design; RF IC building blocks - I9 q* [& ^1 ?2 o

2 F) i3 |$ B# D" z  x  S3.Solid understanding of IC design technology and process/methodology in IC design solutions ! e: G2 s% ^* d- x6 k) g/ j4 l
8 `4 z" w' Q# H- N- R% s
4.Familiar with Cadence analog and mixed-signal EDA tools is a plus
作者: ranica    時間: 2014-8-8 11:39 AM
代理商管理工程师
* c4 k/ l; e$ u$ L
, Z& M' E- ]4 u3 P- }0 ?8 `公      司:IC设计公司
! k; V! b$ w. I* i" N$ b工作地点:深圳# m/ T& {5 N, P' s* ]

( `( l  j& [8 n0 X工作职责: 8 k8 C6 `2 r) I' g1 r0 Q
1、        协助组织每月代理商采购、销售、库存等信息的收集、审核、统计、分析工作;  / n' \- Z( i# C/ l1 z5 w
2、        协助开展和推进代理商开发、续约及终止工作,并负责代理协议的评审; : X! R' D  }3 m  d7 |2 @) z
3、        制定和协助制定代理商发展规划、年度评估与评级、激励与考核管理; 7 U- ]5 J0 q1 Z5 B" @
4、        代理商和公司业务出货事务处理; 5 V! d$ h4 T' T! Q. p# D. P/ n
5、        代理商出货数据监控及核查; 7 b% g) p) }- t; d$ \
6、        公司进口报关工作的受理;
* o# {, }4 c4 n8 @& v7、        协助推进和协调配合其他代理商管理的相关工作
; e3 B; |, b) |0 I. y+ ^2 [
2 }! \2 ]2 c7 e- [$ L岗位要求:
7 b. W6 N( O  W4 b2 v1、良好的数据处理分析能力、文案编写处理能力及整合资源能力;  0 c: E/ s) `% D% [) {
2、具有丰富的渠道开拓与维护的工作经验和商务沟通、谈判经验,具有至少三年以上电子行业代理商渠道管理经验;  
) B% {) \4 |8 W1 [5 ?- U% n3、良好的气质形象,理解力、沟通表达能力、组织与协调能力,较强的情绪调控能力;  
, S9 q8 o) {2 t4、有强烈的事业心、进取心和责任感,有清晰的职业发展规划;  
& _: K. n, ]1 p" e3 G% l5、工作主动性强,诚实可信,执行力强,思路清晰,善于解决问题,讲究策略,对临时性的突增任务有很强的承受能力和包容度;
$ S# i0 g/ O5 m/ m6、熟悉使用EXCEL、WORD、PPT办公软件;
作者: ranica    時間: 2014-8-8 11:40 AM
Field Quality Engineer, Asia
% l# p) k! C$ m4 x' w' I3 q, M' Q3 l0 K- C, d1 l  _/ b
公      司:a world leader in graphite material science, Q8 d' V0 \8 U8 S1 w4 S$ I
工作地点:深圳
# F8 }) L. z1 ^2 L0 K# A9 F: r6 ^" @3 a6 }7 v8 D9 {0 q
Primary Function: : v% C; y2 D3 n1 _" ]- l: ?. N
Carries out Quality functions for AET customers of finished parts, contract manufacturing as well as converters in Asia.
; @1 K& M0 P' X' H" ]. f7 G
8 v0 W- x0 \! R1 }' E4 qDescription of Responsibilities: ) P1 o6 L5 Q2 @, ~* t5 M: H" [
Under guidance of AET QA director:
7 i6 x( y9 u: D! H8 ]' s% I) }?Supports sales of finished parts at End Use Customer抯: & L* p6 W( X6 r4 w1 g6 I
o        Helps turn customer抯 explicit specification and implicit expectations into inspection specifications.
2 I: A* r8 F( H+ k3 m7 I( |) {o        Addresses customer抯 complaints and dissatisfaction in a timely manner, including at the customer抯 site as required. 0 y7 S# a+ ]  F1 W# |" p
o Runs investigations using specific problem solving methodology and manages communication to customers on these investigation and corrective action plans." U# {6 m) ], k
Is responsible for verifying final inspection results of finished parts at our Contract manufacturers (CM):
9 U; K! D3 M  Lo Helps ensure Customer specifications have been consistently implemented and updated in CM documentation system
& g; k) M  v0 ]; B3 T  I' Jo        Audits CM final inspection procedures and results
3 U% A' s  f  R8 F; Yo        Provides our verification of CM inspection results for prototype, pre-production and production stages. ( Q; C: S0 I3 y7 l* g$ B  ?
o        Monitor抯 CM抯 Outgoing Quality control records, analyzes yields, identifies improvement opportunities. / }3 n9 m0 A" P0 D0 ]3 n; Z  }
o        Drives Customers?complaint investigation at the CM抯.
! R) {8 r- I" X& z) N, i6 g' L7 K+ R0 Z?Supports sales of semi-finished products  at converters
3 |" R9 b& k0 V* T8 {2 c# co        Helps identify true end customer抯 needs as well as converter抯 needs and develop specifications.
% i# A7 @) e( h0 Y5 D7 Zo        Helps optimize specifications for semi-finished products so as to optimize the whole supply chain.
2 p2 C1 I9 o) F. U/ p6 g1 vo        Addresses converter抯 complaints and runs investigations using specific problem solving methodology.
作者: ranica    時間: 2014-8-8 11:40 AM
Works in close relationship with: Integrated Solution process engineers, Lakewood (USA) plant Quality manager/engineers, Regional Sales Managers and Application Engineers.- h+ {( G' `6 F% J- g9 l
3 v" k  S3 Z) G) X& m+ Y
Competencies: ; k( n& j: P5 G/ M( O. {- |
Customer focus
* X8 G" J# H: V6 j1 j* N8 EProblem Solving 9 `. l) `% A" Y0 c, J1 ]
Sense of urgency/priorities/ Responsiveness 9 t9 i3 [: O/ n# V5 I# h
Attention to details
3 e4 V. [7 D+ b. VFunctional/Technical Skills  & v- F9 M3 ~1 l8 q
Flexibility " C$ Q3 |& f6 G  p% x8 E7 R0 ^
Integrity and trust4 ~1 k: E+ ?1 W' m
9 {" r4 t. s, c; `; F+ }7 N" R6 e
Knowledge / Skills / Experience: - _) r. K' I) m$ H
5 years Engineering degree (mechanical degree)
7 a3 z5 x2 _5 I3 p1 {Mandarin as mother language. Fluent English (written, spoken) is a must. Korean is a plus. " ~9 u+ P: ?5 S4 W) _
Good background in Quality system (ISO9000), Experience in Lean 6Sigma is a plus.
( z) F! [8 s- ]- ?% k% U4 f6 n6 CMasters Quality tools as problem solving, standard work, and statistical analysis.
# v4 ]8 {, V! G  U% LAbility to use Solid works is a plus.
5 C- R' N7 b5 d: u' \% F9 U
+ L% o2 \$ h6 NWorking Conditions:
8 ^8 Q6 v8 d  F. F. BSignificant travel. 75+% of time. Mainly in China. May include travelling to the USA, Korea and other countries in Asia./ N/ {- R1 v* e, G, G% J
Office and manufacturing (die cutting, lamination,..) environment at our customers/CM.




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