標題: What Verification IP do you plan to use MOST on your current design? [打印本頁] 作者: atitizz 時間: 2013-9-5 03:34 PM 標題: What Verification IP do you plan to use MOST on your current design? Please indicate whether the IP exists internally or is purchased from 3rd-party...: n) u6 Y3 K+ H5 n+ m4 t
4 g* O6 T0 M% J+ B" \" ROther (please specify):作者: ranica 時間: 2013-11-11 10:53 AM
ASIC工程师 # Q# V: O- m7 a公 司:High-technical IC supplie with commercial FPGA intellectual property 2 X; K# ]# Y( u$ U9 M/ N: V0 H) h; a4 I工作地点:北京 # \* ^, v$ v. h# J/ c5 Y: N; R+ K& o y/ V s0 j- {4 d
职位描述6 H1 B: G1 W5 f4 t
1.微电子相关专业硕士学历, 3+年ASIC前端工作经验(不含在校、实习); 5 I6 F9 t$ m2 o: `, P$ K* J2.熟悉并参与过ARM或MIPS等常用SOC架构的设计、应用,对SOC架构及常用外设的工作原理有深入理解。 ' E* J1 E( D) k4 a8 m8 G3.精通verilog语言,能够独立完成verilog module design,拥有良好编程习惯codingstyle。 , o- G2 z5 a ~4.能够独立完成单元级仿真,在系统仿真中承担部分工作。 : K( i2 B& d# x+ i' b! T6 n; y
5.至少1次成功流片经验。 ; S X& x4 d& I3 S6.对synthesis、sta、dft等有一定了解。 ( t1 ~: A% n* c. v7 t8 @
7.良好的团队合作精神作者: ranica 時間: 2013-11-11 10:53 AM
职位要求 2 T+ v- E: N! l# E4 F @全部或部分满足以下条件者优先考虑: 7 ~( k9 u! U& V9 ?4 X L
1.有在大型asic公司工作经验,深入理解其企业文化。 : O3 U v# F! D' C7 `' d2.熟悉验证方法学;熟练使用SystemVerilog等专用语言进行验证平台的搭建和维护。对Testcase规划、覆盖率分析、门级仿真、ATE testpattern产生等有实践经验和深入理解。 8 W2 w7 K: Q5 e& X, H1 {; D3. 丰富的fpga emulation经验,能熟练进行板级debug,编写调试简单driver。 " D# w/ s" k# a, N3 H
4.对芯片系统架构有一定理解,能进行子系统级别的独立规划设计。对以下知识中的至少2种有实际经验: # }- H( Y" {1 Y
ARM/MIPS/8051 CPU及其架构, 1 w& V: ~) q3 W# w5 M& hAMBA(AXI/AHB/APB) 总线、OCP, ) ^$ q- R- W' E& T& @
USB(3.0/2.0/1.1, 5 J1 ]7 y2 F/ U9 M) rNAND/Nor Flash/S-flash controller 5 j( t* s* I* f4 P5 e$ a* ]$ I: L
DDR(2.0/3.0)controller/PHY - v( }. U( P3 |low power design, 1 h7 K6 v1 ?! t4 |chip level clock/reset generation and control, 9 I! q9 V! `2 @! f! I. O6 x
SD card controller, SATA,sim card ; W4 j8 y: Q }6 Ssoc基本外设 (SPI/ GPIO/timer/WDT/I2S(SSI)/I2C/UART), + X v) t+ o- f7 z
Ethernet, 1 B% {1 u& p) E: FJTAG, etc.作者: ranica 時間: 2014-2-11 02:52 PM
FAE: ]6 b; w0 U0 D% F+ _
公 司:A famous IC company & G" W# D8 A5 u; g5 s" Q工作地点:深圳 6 H+ K+ q# ~; D/ a) W - M2 ?2 k8 g# p3 T1 qKey Responsibilities * P! V' X; P! @% _. ]. \1 i: Q9 z3 l6 i* }0 n; w$ u6 q
Scope prospected and qualified IP opportunities develop strategies and processes to increase IP licensing and design wins opportunities. / e6 i+ b+ J+ X
; J# B: i+ t1 I* V# VRemove technical obstacles and provide a path to increase IP licensing and design wins opportunities. 2 D% h8 o6 C# z6 Q- U
# U8 q: X/ g! [4 k# ~& |" Q2 C0 cPresent and demonstrate technical details of xx products to customers. # d7 D! R$ Z$ V# N; N/ F' T1 G+ C 6 e. M: S- _% GProvide technical support in pre-sales opportunities as well as ownership of customer support process. . G% P2 V$ G1 b+ f( f 0 Z# I, B* r8 \" @- ~/ uProvide appropriate product recommendations to meet customer requirements , R$ n% S8 p5 ^& r7 x5 I 6 L7 U' d) A; J9 k. U& f1 L; u) UProvide system design expertise and first pass architectural planning for products in early design stages作者: ranica 時間: 2014-2-11 02:52 PM
职位要求 - H9 s0 ?/ f# VEducation & Qualifications ) {8 c1 |& ^5 |- f5 x
Qualified candidates will have a good university degree in Electronic Engineering, Computer Engineering or Computer Science. Master degree is a plus. : \' f1 y* V* s" ^' C- @2 k5 c7 ]' t" K- W( g9 P
Professional Skills and Personal Requirements 7 @+ b% z J! v1 b4 uExcellent communication skills 2 s8 n W6 u) w/ h, mHighly self-motivated with the ability to effectively work alone as well as in a team * C' x, o2 w! o+ I! eMust have the desire and ability to solve problems quickly. ) B4 r* @' k O1 HDemonstrate a positive attitude and respect for all members of the team ' w. P& W% M4 x j# r. E3 i
Be motivated to continuously develop skills and accept a variety of responsibilities as part of contributing to the team’s success - L! W; x1 T/ J8 PWilling to travel both domestically and internationally, approximately 30% of time, spending significant periods of time on customer sites and for learning trips. ( [- u) o% E, ?" t$ u# U6 {Good spoken and written English + S! W% Q# m; c, H4 v- s. t1 Y
Customer related experience is a plus, but 10+ R&D experience is must-have. ; f6 F8 P. ^3 a( B# b% N- f+ i. O; t: f; _1 M, Q
Essential Technical requirements , s A$ _ {5 n- r$ G4 c- B
7+ years experience in IC hardware design. xx SoC tape out experience is a plus. # n4 }* d# b) {% h, F
Working knowledge of ASIC Implementation (Verilog, Synthesis, P&R, and Timing analysis), including relevant EDA tools and methodologies.1 _4 S2 Q" C! O% w: T9 u5 v7 I! A
Experience at the system architect level with intimate knowledge of bandwidth analysis, low power design, performance optimization etc ' K9 }/ F# ~" Y( T Z* S% n( qGPU experience is a plus. . c8 k- T7 f# J# q# ]# w
Consumer application experience is a plus作者: innoing123 時間: 2014-2-27 01:35 PM
Brocade在其數百萬兆位元(Terabit)核心路由器中整合了Altera的120G和150G Interlaken IP ( P6 T$ ` q: X) R1 D採用含有Interlaken IP的Stratix V FPGA,Brocade線路模組能夠靈活的根據雲優化網絡進行擴展 1 @- X% X8 A2 b( ^8 t/ E |7 o9 [# P4 w2014年2月25日,台灣——Altera公司(NASDAQ:ALTR)今天宣佈,其Interlaken矽智財(IP)核心通過認證,被Brocade® MLX®系列數百萬兆位元(Terabit)核心路由器選用,開始產品發售,應用於資料中心。Interlaken IP在Stratix® V FPGA上實現,有助於Brocade路由器快速高效的擴展雲端最佳化網路。使用Altera FPGA和IP來擴展雲端最佳化網路,支援企業管理大量的網路資料,並根據結果即時做出決定。1 U( L9 ]3 F2 ?
# \, V t' M) y" z- FBrocade公司ASIC和硬體工程副總裁Majid Afshar評論表示:「Altera為我們提供的這一種Interlaken IP設計能夠非常靈活的進行配置,而且非常可靠,滿足了我們各種線路模組配置的寬頻效率需求。這種獨特的配置設計結合我們的服務成本模型基本結構,讓我們的企業和服務提供者客戶獲益匪淺,他們對預算要求非常嚴格,而且需要的服務比較特殊。Altera的Interlaken IP頻寬可以擴展,具有很高的資料效率,滿足了客戶對大資料的需求,同時也滿足了需要透過網路高效率傳輸資料的其他應用需求。」3 j x! m2 o! Y" U8 N. E
* B/ u+ |. n7 f4 D' NAltera採用Stratix V FPGA架構的Interlaken解決方案支援速率高達100 Gbps以上的晶片至晶片資料封包傳送,協助OEM傳送每天產生的近2.5艾位元組(exabytes)資料。Interlaken IP是完全整合解決方案,包括了MAC、PCS和PMA層。作者: innoing123 時間: 2014-2-27 01:36 PM
Brocade採用Stratix V FPGA架構的百萬兆位元路由器解決方案為企業決策層提供了:( r. H+ O- z( W9 t+ ]
/ Q1 Q( j3 H7 Y7 S' {# D5 `: F: l岗位要求: 3 _! L' T, t, P1 @& Y1. 计算机、电子类相关专业,本科及以上,三年工作经验; 2 j5 W2 {) r5 Z$ ]2 z- ?7 s2.精通C/C++语言,数据结构,丰富的产品应用开发经验; . O. `" O: u. k5 o/ |- S3. 至少对一种嵌入式CPU(CCORE、PowerPC、ARM、MIPS等)有深入了解和实际产品开发经验,熟悉PowerPC架构者优先; 1 p( a5 G1 D3 A- e- e4. 熟悉硬件IP,如PCIE、USB、DDR等,有相关IP测试经验; 5 A3 C |1 m/ g5. 工作扎实认真,服务意识佳,善于与人沟通,具有团队合作精神、能够承受高强度的工作压力;作者: ranica 時間: 2014-5-30 11:34 AM
IP验证工程师 - k, { k$ D9 z; G) B; I公 司:A famous IC company! o# a: q$ _" }( B) F
工作地点:苏州 . A Y# R' O% b# U ' c# r4 l: i, G- I. ^! H+ q职位描述: $ f% h5 c7 i+ C7 [ k1. 负责PowerPC等平台上的软件设计、开发、测试 4 R* _/ Y( A; f$ x( S
2. 配合IC设计人员完成芯片开发验证工作 9 P& a! \; D7 L5 U; J3. 负责相关技术调研,编写相关开发、测试文档 9 ?* b( V% K$ O8 t% c
4. 负责芯片及应用方案的市场推广和技术支持工作 8 Y5 j! S+ T& f; k: C0 @ ! V4 \) r; B& }4 N+ K岗位要求: ) B& G8 G' h! {0 F" k6 `1. 计算机、电子类相关专业,本科及以上,三年工作经验; : @- z* [/ T" A2.精通C/C++语言,数据结构,丰富的产品应用开发经验; . L. \4 V0 a1 j6 F1 E3. 至少对一种嵌入式CPU(CCORE、PowerPC、ARM、MIPS等)有深入了解和实际产品开发经验,熟悉PowerPC架构者优先; 6 q7 ]. `, I, f) }4. 熟悉硬件IP,如PCIE、USB、DDR等,有相关IP测试经验; & K: g2 i1 l" @% I7 Q0 g5. 工作扎实认真,服务意识佳,善于与人沟通,具有团队合作精神、能够承受高强度的工作压力;作者: ranica 時間: 2014-7-16 08:19 AM
ASIC Verification Engineer (WMAC) " i$ l4 N+ `& k4 y+ G& t6 H+ j( @ 8 r* P* U+ Q7 h. |/ Y公 司:A famous IC company# v% v" J& \5 B* |5 F& f
工作地点:上海* g( f$ M% W! y# r$ O5 b
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The Role: 4 _) s. H! @- k, U8 W
ASIC design and verification 0 g7 D9 k2 r7 F1 ?! E, c: S/ h Work closely with the California teams + y9 K! |. ?' y% l( q: j; a Support chip tape out and bring up " e! W" o k6 T
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Requirement: / e% F" Z' u% G
8-10 yrs. experience + M/ l* D6 }- w0 }2 Y Knowledge of Verilog / System Verilog & Perl " Z9 i* f: }8 v+ }. ^: z* H0 o Has worked on complex project; experience with 802.11 is preferable 1 q; @1 l a) M, N" `
Can work independently - want him to take over MVE 3 H. `# `" w% I. u5 Z3 U5 y' S Experience in Networking SOC, Ethernet MAC or any other MAC layer protocol experience is plus作者: ritaliu0604 時間: 2014-7-17 09:32 AM
ASIC Verification Engineer (WMAC) $ Q& l. X) _0 I$ p6 d: n 7 }9 H+ \( H. w. W0 X! u公 司:A famous IC company 5 U: Y: N2 T1 e- ]/ `8 B工作地点:上海$ x0 r! S" q4 }5 |8 n# M
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The Role: & r, x& B# r9 I4 k7 P7 A
ASIC design and verification & o( P# Q/ F4 \9 `& H+ D
Work closely with the California teams ) F& X8 P! }2 W Support chip tape out and bring up " ~+ v% X0 K( U/ y) Y/ t
5 Z9 B, r! D- j! B
Requirement: " u0 G) o6 S$ A& `
8-10 yrs. experience , I; u& A {5 t7 [% H Knowledge of Verilog / System Verilog & Perl - ~" `- b$ o& q+ d
Has worked on complex project; experience with 802.11 is preferable 7 X* r3 F3 ?% e Can work independently - want him to take over MVE 3 c) P3 X, @2 ^' O- \ Experience in Networking SOC, Ethernet MAC or any other MAC layer protocol experience is plus作者: sophiew 時間: 2014-7-25 10:56 AM
Job Title igital verification Engineer $ s6 ~* G( o0 M" T* W: c8 H9 PJob Category :Semiconductor : L/ h3 I1 y% R, I% [7 ]Location : Singapore6 z3 s) L2 l% W1 l
Job Type : Permanent % Y8 Y8 [9 \" E0 B" Q6 XJob Description: # N1 I; Y) W, O! G$ A* SLooking for SoC Verification Engineers Experienced in System Verilog Tools $ ~- ^4 ?- W. f$ ^5 D* S c+ y: ]( v( B" o1 [. GResponsibilities: # y d+ v' o- E( h! VConstrained-Random Verification using SystemVerilog.1 s; G& ~* y. G1 B2 p# B: `: U
Develop verification environment for DUT,Write and debug tests for DUT using SystemVerilog, Perl, and C. ; F3 E# x' T0 j% O- d" u( yDevelop Bus Functional Model(BFM) or using Verification IP(VIP) for tests: K7 M+ d* t9 V7 H# ]) ~
Developing and reviewing test plans 2 m/ l( B4 b( K5 r% ~4 e3 DWrite coverage monitors to evaluate the coverage of the DUT.4 m: u; K) P: T8 K @" Z% }5 Z
Formal verification using SystemVerilog Assertion to verify SOC or IP is plus4 x% X" M& C: h v* q5 d
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Requirements:# |4 n( h+ s8 \* M% }# p1 _
>4+ ethernet switch background * G) C6 E, x' z' T6 r+ m6 {# V+ tAt least 3-year+ experience on digital design and verification- u7 ^1 a% b2 Y
Experience on SystemVerilog/VMM/OVM/UVM (UVM is plus) A3 d- p1 p! E
Familiarity with transaction-level verification at higher-level of abstractions is plus.+ `. Z5 x G" ?5 v: @# o, M* Q
Experiences in developing measurable verification plan. ; D Z( e$ w/ {' _) WProficiency in UNIX scripting languages and utilities such as csh, sed, awk, and Perl.