5 X8 j/ ^6 E* P) L' { & X- S8 q5 T3 u5 R•The Digital ASIC Design Engineer will be part of the team responsible for the design and development of capacitive and/or piezoelectric MEMS interface ASICs. He/She will the responsible for the digital blocks including serial interfaces, control logic, DSP blocks such as digital filters, feature detection logic and other digital application accelerators. + @+ N0 h9 E' n/ l1 n
•The responsibility of the Digital ASIC Design Engineer includes scheduling, design, simulation, synthesis and layout of critical circuit blocks, including pre- and post-silicon verification. + j) q% F$ T1 U. H0 B7 ~
•It is also expected that you will conduct periodic design reviews, including with application engineers. 3 A) ~& b e6 R5 i J$ f" L/ \ ) u# i& U! z# |# s( P( @& c# A1 t: |( w7 H+ P Requirements:4 p3 |/ x9 O4 H" \1 L. b: U
T: M& l2 _3 O
5 o6 {( _* i, `( o0 |
•Master/Bachelor’s Degree in Electronics/Electrical Engineering. 1 F, b5 v* e# F
•Minimum 1 to 3 years experience in Digital ASIC design. . n( {% k* x/ d3 p$ t•Very good knowledge of CMOS processes. 2 F9 t. h4 W0 m5 ^& Z& ]
•Highly proficient in modern ASIC design tools, both frontend and backend. % i: Z0 V! p9 W. p
•Experienced in design of I2C, SPI, control logic and DSP building blocks. * B" b4 U& b. [3 z8 w0 r6 x•Skilled in laboratory testing of IC prototypes. 0 v, K4 b. ^, H" i9 Q$ P5 C6 y•Able to develop circuits from algorithm to synthesis. * _: T% ~. \1 b' s" V•Knowledge of Linux operating system required. 1 ?+ j' ]& E4 a+ y1 E' o5 X, {•Experience in MEMS interface ASIC design advantageous.. o' b! M8 \' S* d$ h# G
% T3 j* {" }- r0 Q