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標題:
VHDL新手上路,程序Bug請教
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作者:
ultraman
時間:
2013-10-18 09:15 PM
標題:
VHDL新手上路,程序Bug請教
一般dly'event and dly='1'是不能寫在case裡面嗎?
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因編譯會出現以下訊息
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Error (10822): HDL error at CUB.vhd(70): couldn't implement registers for assignments on this clock edge
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Error: Can't elaborate top-level user hierarchy
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Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 15 warnings
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Info: Allocated 144 megabytes of memory during processing
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Error: Processing ended: Fri Oct 18 21:24:23 2013
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Error: Elapsed time: 00:00:02
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Error: Quartus II Full Compilation was unsuccessful. 2 errors, 15 warnings
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程序如果寫的不好,可以幫我改寫,因是自學,所以比較少機會可以看到其它人的寫法!
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Library ieee;
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Use ieee.std_logic_1164.all;
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Use ieee.std_logic_unsigned.all;
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Use ieee.std_logic_arith.all;
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Entity CUB is
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Port(
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sv_ctrl,coll_manu,coll_auto,count_v2,T1I,T2I,dly:in std_logic;
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count_clr,coll_up,coll,cold_pin,T1O,T2O:out std_logic
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);
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end CUB;
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Architecture cub_arc of CUB is
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signal d : std_logic_vector(2 downto 0);
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Begin
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proce1
rocess(coll_manu,coll_auto,count_v2)
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Begin
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if coll_auto='0' then
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if coll_manu='0' then
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if count_v2='1' then
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count_clr<='1';
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else
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count_clr<='0';
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end if;
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coll_up<='0';
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coll<='0';
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cold_pin<='0';
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end if;
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end if;
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if coll_auto='0' then
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if coll_manu='1' then
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if count_v2='1' then
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count_clr<='1';
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else
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count_clr<='0';
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end if;
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coll_up<='1';
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coll<='1';
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cold_pin<='1';
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end if;
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end if;
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if coll_auto='1' then
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if coll_manu='0' then
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if (sv_ctrl and count_v2)='1' then
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case d is
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when "000"=>
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coll_up<='1';
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T1O<='1';
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d<=d+1;
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when "001"=>
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if T1I='1' then
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T1O<='0';
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coll<='1';
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cold_pin<='1';
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T2O<='1';
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d<=d+1;
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end if;
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when "010"=>
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if T2I='1' then
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T2O<='0';
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coll_up<='0';
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coll<='0';
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cold_pin<='0';
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d<=d+1;
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end if;
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when "011"=>
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if (dly'event and dly='1') then
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d<=d+1;
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end if;
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when "110"=>
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count_clr<='1';
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d<=d+1;
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when "111"=>
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if count_v2='0' then
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count_clr<='0';
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d<="000";
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end if;
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when others=>null;
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end case;
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end if;
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end if;
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end if;
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if coll_auto='1' then
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if coll_manu='1' then
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coll_up<='0';
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coll<='0';
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cold_pin<='0';
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end if;
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end if;
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end process proce1;
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end cub_arc;
作者:
stroke
時間:
2014-11-12 10:14 AM
你有打錯
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Library ieee;
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Use ieee.std_logic_1164.all;
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Use ieee.std_logic_unsigned.all;
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Use ieee.std_logic_arith.all;
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Entity CUB is
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Port(
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sv_ctrl,coll_manu,coll_auto,count_v2,T1I,T2I,dly:in std_logic;
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count_clr,coll_up,coll,cold_pin,T1O,T2O:out std_logic
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);
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end CUB;
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Architecture cub_arc of CUB is
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signal d : std_logic_vector(2 downto 0);
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Begin
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process(coll_manu,coll_auto,count_v2)
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Begin
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if coll_auto='0' then
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if coll_manu='0' then
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if count_v2='1' then
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count_clr<='1';
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else
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count_clr<='0';
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end if;
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coll_up<='0';
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coll<='0';
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cold_pin<='0';
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end if;
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end if;
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if coll_auto='0' then
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if coll_manu='1' then
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if count_v2='1' then
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count_clr<='1';
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else
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count_clr<='0';
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end if;
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coll_up<='1';
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coll<='1';
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cold_pin<='1';
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end if;
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end if;
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if coll_auto='1' then
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if coll_manu='0' then
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if (sv_ctrl and count_v2)='1' then
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case d is
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when "000"=>
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coll_up<='1';
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T1O<='1';
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d<=d+1;
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when "001"=>
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if T1I='1' then
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T1O<='0';
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coll<='1';
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cold_pin<='1';
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T2O<='1';
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d<=d+1;
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end if;
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when "010"=>
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if T2I='1' then
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T2O<='0';
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coll_up<='0';
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coll<='0';
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cold_pin<='0';
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d<=d+1;
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end if;
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when "011"=>
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if (dly'event and dly='1') then
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d<=d+1;
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end if;
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when "110"=>
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count_clr<='1';
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d<=d+1;
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when "111"=>
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if count_v2='0' then
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count_clr<='0';
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d<="000";
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end if;
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when others=>null;
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end case;
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end if;
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end if;
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end if;
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if coll_auto='1' then
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if coll_manu='1' then
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coll_up<='0';
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coll<='0';
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cold_pin<='0';
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end if;
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end if;
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end process ;
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end cub_arc;
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