Module name | my_pipeline | |
Signal | Direction | Description |
clk | input | System clock |
rst_n | input | reset signal, active low |
d_in[15:0] | input | DUT input data |
d_rdy | input | DUT input data ready |
d_full | input | The next stage data full signal |
pp_d[15:0] | output | DUT output data |
pp_rdy | output | DUT output data ready |
pp_full | output | DUT full signal to preceding stage |
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