標題: 靜電放電測試 [打印本頁] 作者: ritafung 時間: 2008-4-12 12:55 AM 標題: 靜電放電測試 剛剛研究了靜電放電（ HBM ＆ MM） JEDEC標準，實在需要很長的時間去進行測試。假設該IC具有數以百計的pin，很可能將需要超過1個月完成整個測試。這裡是否有任何人負責做ESD測試？作者: m851055 時間: 2008-4-12 08:07 AM
竹科閎康科技有此業務 , @- F5 ?1 y: M- U電話在網頁就查的到了.......................作者: cuban487 時間: 2008-4-12 11:12 AM
很多實驗室好像都有,但都在台北.( K8 M1 E7 `& A) W
儀特好像就有可以去查ㄧ下作者: kyyyyyykimo 時間: 2008-4-16 01:02 PM 標題: 很多家實驗室都有啊 目前新竹地區有"宜特"與"閎康"兩家比較大 $ q; H. p! v4 g _( v我的建議是去閎康，會比較適合。 + C. |8 C6 J: M; c因為我本身工作性質也是有接觸到ESD測試, j1 [* A8 {. n# b2 F$ A
測試多Pin需要花費時間比較長久，可是你們HBM是使用JECDE, ^' h8 C9 z' Q
在Zap的次數明顯比軍歸來的少了。 1 b6 o7 n, P4 m6 b5 S$ U) p! W作者: ritafung 時間: 2008-4-22 12:07 AM
my company is pursuading to MIL-Std ... # S5 z, k% ~: R3 ^actually any company need MIL-Std? Our application is not for military purpose....作者: wesleysungisme 時間: 2008-5-21 12:14 PM
For ESD test (HBM) & p) ]8 @8 \- L% U3 h6 DThe following are the test combination: 2 _8 d6 J9 G6 a5 V! ]4 k H* D/ v1. Power to Power- `) B, q u+ M8 T+ j5 A1 c
2. Power to Ground/ @: e( j: G) e- Y) J$ d8 t
3. IO to Power 1 v& J0 H9 c( `0 q. B. S4. Io to Ground ; ]+ h R# T2 w; [, e& e5. IO to IO7 v- d( w5 z8 v+ f
(different power domain need to be treated as different power. For ground usually you can treat as one group_silicon use substrate as common ground. But if you measure two different ground pin/ball > 2ohms. It should be seperated as 2 grond.)- {# O; Q9 _+ E( l) h% g/ U
, J" ~$ t7 \4 O. y1 N+ g- @the total zap time fomula will be~ 2(+/- polarity) X (IO#X(P#+G#)+IO#+P#X(P#-1)X(P#-2)X...X1+P#XG) / _4 c% }" g2 O" w! j9 ~: k2 IFor example: You have IO1/IO2/IO3/P1/P2/G1* |4 @4 U; b K: J: d# k6 }
2x((3X(2+1)+3+2X1+2X1)=25(multiple the zap interval)1 F* R+ U# ~0 N8 d0 ?
So for high pin count it will take a lot of time. But it won't take more than a week(for one chip). ; B0 `* D- X( a
1 x9 p" p6 C7 M0 i* B' D0 c
For your reference.作者: f5882077 時間: 2008-5-23 03:02 PM
樓上的Jason...據我所知大部分的IC設計都會跑去宜特做ESD...為什麼你要特別建議去閎康做呢??" U5 V( j% \$ Q
有什特殊原因嗎??會比較適合的邏輯是什麼??是否可分享一下心得??感恩~作者: ritafung 時間: 2008-5-26 09:15 PM
thanks wesleysungisme for your answer. : ]3 I" l& [) e# }as our pin count is over 1000 and no. of power is ~ 20, so it's quite time-consuming. 0 z: W r' t! S' p% i C' J( N
and there is technical issue about bonding all the dies into COB for ESD zapping, i wonder if anyone could share their practise? we feel difficult to strictly follow JEDEC standard.
