% Z+ z/ I8 t- p工作经验: Y( X( q: n3 N
2年以上工作经验, 具有扎实的CMOS基础知识 & X% k2 e2 R9 E4 J0 w3 j2 _0 Z e5 U" v' w5 z
学历/专业 w2 v/ u) |; d* k0 H
E.E硕士学历作者: ranica 時間: 2013-5-23 04:03 PM
Staff PnR/CAD Engineer1 C7 F- j- V7 \3 i+ y) j8 j
公 司：NO.82-A famous IC company. W& }# X( n3 B6 u; b* g8 Z, e S
工作地点：上海 3 g5 |' B6 j% T# N0 Q0 {+ U2 g$ c" `0 i" @& R
Responsibilities0 r5 b/ m5 }( G& V) ?
1. IC Place and Route for designs up to a few million gates in deep sub micron technology, with advanced low power flow; Timing, Power, IR drop and Noise analysis # u7 F) ^/ g* Y2. DRC/LVS command file, rule deck and chip tape-out handling and support; % q3 m, U+ g- M1 a! D% ~1 C+ s6 ?3 \: }3. IC-CAD tool and design flow support 6 Z2 G: a1 {# Y1 a2 \$ _! R. C% G% y4 Y) `
Mandatory Skills3 L- Q: L9 C3 H8 s. @% w
1. Place and Route in deep sub micron technology; timing, power, IR drop and noise analysis3 t1 F. [/ W; m/ e
2. In depth understanding of IC layout and command files, IC process flow * ^/ ]; w* k4 s% o/ G4 ~6 ]% i3. Good knowledge of Linux/Unix and ICCAD tools 3 `2 y5 I2 K! E( g8 ]1 ^4. Good knowledge of digital and analog IC design flow) o$ v4 C& _( e! Y7 m2 A
5. Scripting language and file/database conversion techniques. _5 B9 }7 l: A/ H9 ?. y
6. Fluent in English* X2 s( b6 ?0 y$ Y( |
$ I- l( i. ^# u+ B/ F0 g. G, S5 z% T
Preferred Skills, A8 _; [7 h: Z: g
1. IC hand-crafting layout design 8 l9 m& ^- E5 X( ~" m: j2. VLSI design and verification$ b( a! k! l# A$ j: M
3. Library design and characterization; m, z- O" [$ s, [4 X
6 k2 b ?& T+ D- ~- d
Education) S9 | r. R$ p) {
University Degree of Microelectronics, Electrical Engineering or Computer Science, 9 l0 m7 n5 G* @# G! H6 e: Z9 RMaster degree preferred* W; K" {2 b7 E, }
/ I# i% i2 y) \4 N' B# f
Experience9 H, L" E# t0 ]0 F' d" d5 ?
8+ years of working experience, 2+ experience in US or Europe based ICCompany. 3 h8 W% Z, L: g g6 _* w( S3+ years of experience in Place and Route 4 E* q! Z6 S; ~; C7 T* `3+ years of experience in IC-CAD, CAE or tape-out handling作者: ranica 時間: 2013-5-24 01:41 PM
CAD Engineer/ `! F' z+ k4 q% ~9 [; x4 k
公 司：NO.25-A famous IC company `- ?5 Y" g+ q工作地点：上海 $ R2 L4 u% B: t% |; `9 b$ r4 w: f5 T5 H2 d. q. I5 f
Job Description: ( [+ d! G4 K0 \Provide first-class system administration services to engineering community& {5 r* ~" H* D0 z5 x; x
Install software, apply patches, manage file systems, monitor performance and troubleshoot users’ login - E( V+ S- L8 O8 Yenvironment.$ x& b: a( ] |% l2 ]
Perform system failure analysis and recovery to insure consistency and integrity of file systems.1 d, O& Z$ ?+ }% u3 d
Set up and configure hardware and software for user workstations as well as enterprise servers. \# C9 m& L2 r6 z6 s& d* {( KAutomate administrative tasks via scripts and cron jobs : O- i& ?, W1 kLiaison with vendors and support evaluating product procurement.) O( K/ ~4 H$ J+ H1 o
Support main stream EDA tools’ user interface- L$ y% B4 @0 S/ G
9 g0 b) o1 y# H) l6 oJob Requirements:2 I5 k' w4 ]" i2 t
BS degree in Computer related field# B7 {/ r4 E3 `/ w0 S' l) O
3+ years of relevant experience" V- v. Y( @+ s, y9 V: n# v, O, d
Hands on experience with scripting and NIX operating system 3 K5 a6 c& q6 z; B L# QProficient with CAD system administration tasks. E; R4 o& I# G: ~1 w/ m6 o3 A: O
Knowledge of X-windows programs (VNC, Exceed, ..) and file-sharing utilities (SAMBA, ftp, ..)# w% Q& h0 y# }
Excellent written and verbal communication skills G$ B( L( r# C$ qFluent in English, t7 d3 i% A) E: F5 x+ Q* b+ m# a: l
Self-motivated, team oriented and professional ethic作者: ranica 時間: 2013-6-7 05:32 PM
CAD Engineer6 g ?, n/ f& q) l$ s/ r
8 B, y! `! P, I, N! T5 n公 司：NO.25-A famous IC company % u. S/ }4 N) M$ o( f工作地点：上海 p0 V, E9 I( z5 b" s: w' C/ U5 p* A! R0 t
Job Description: I9 ? Z9 F3 f5 eProvide first-class system administration services to engineering community " d3 Z, |7 ?6 w, B! Y; U2 EInstall software, apply patches, manage file systems, monitor performance and troubleshoot users’ login ; _0 \5 I9 G- Nenvironment. % X! L# C5 `, j4 b: c' D
Perform system failure analysis and recovery to insure consistency and integrity of file systems. - o6 i: u5 z1 u- q% |( b' S: A6 z1 S
Set up and configure hardware and software for user workstations as well as enterprise servers. 6 \# n: O$ M' n3 W* F- @, E* G( RAutomate administrative tasks via scripts and cron jobs 7 z; |# z* Z6 h! \( @
Liaison with vendors and support evaluating product procurement. & B0 }8 a2 A [7 X3 J; O
Support main stream EDA tools’ user interface0 d" X5 a/ i# E
5 ]7 {! n# n- ?$ Q( ?Job Requirements: 1 ~' a3 K5 k9 g' N9 w# B
BS degree in Computer related field ; e' K7 Z4 p5 t% _* n9 P$ h3+ years of relevant experience - o& S* `5 K% ?: e0 i% rHands on experience with scripting and NIX operating system - @ Q+ ^2 }& `; |0 n( K* y* b' d
Proficient with CAD system administration tasks 2 L& _ }# i) ?& F- z' o
Knowledge of X-windows programs (VNC, Exceed, ..) and file-sharing utilities (SAMBA, ftp, ..) & d4 j, d, T B4 y8 m0 a. q! A
Excellent written and verbal communication skills " n5 i4 l* }; f# U7 K7 W/ xFluent in English 0 a- y8 { l* ?$ `- Y
Self-motivated, team oriented and professional ethic作者: ranica 時間: 2013-6-13 10:59 AM
Lead Implementation Services Engineer（Shanghai）9 G2 v2 b- f8 \
1 ?4 F7 S8 [9 e# N3 ?: ?) R9 D0 Q公 司：NO.73-One world top EDA company ! w! h0 C- _3 E1 Q6 [9 _) r: l工作地点：上海% T0 G) |5 X( D
1 D9 H, g4 w6 z) l7 ^( H, B8 \职位描述' l; u& ] }& w- B# e/ x" `
1.Ability to handle large sized design implementation tasks & architectural tasks alone. 0 u' Z( D. i; J% N2.Ability to assess Customer''s Design environment, to understand his application needs & to build new Design environment based on specifications & available Cadence tool technology. ! x3 t* r; z6 ~( R; `3.Ability to acquire a basic understanding of the (services) business environment of Cadence within 1 month. / _2 d0 Z. i2 \) J2 M& J4.Working on multi person projects of varying complexity, working especially in a multi-site/multi-cultural project. The latter requires good communication skills in English. : [! y$ J/ D1 i4 ^ b H2 B
5.Feeling responsible for technical delivery as well as business development & opportunity creation. Behavioral competencies: Teamwork; Customer focus; 6.Accountability; Communication; Coaching & feedback; Employee development; Leadership. + R F& X! P9 z, l+ |3 @+ s
1 Y3 @0 h5 N6 D2 f; O职位要求+ L- m* g1 Y) e0 J
1.BS degree with 10+ years of applicable experience, MS degree with 7+ years of applicable experience in electrical engineering, microelectronics. 5 ^$ d4 B, A0 n$ b" }+ V6 l8 n- o2.Essential that the individual demonstrates strong communication, verbal and written, and project management skills. y; Z0 n$ `, `! ^! Z0 O
3.Requires good communication skills in English.作者: ranica 時間: 2013-7-2 10:08 AM
Staff/Senior CAD 2 a/ |+ {. A8 r$ ?. q公 司：A famous IC company. ^/ }% y6 H. e! }: M6 S
工作地点：上海 ) ^+ n! ^ t7 m# k/ k 9 m. ?0 M( b9 H: B7 VJob Duties: 1 X6 U6 o' p4 P# G- _% y& x JThe candidate will collaborate with Sunnyvale CAD team to support Shanghai design center. 4 L. t! l% i0 b( r3 e# l a
1) Industry leading edge ASIC design flow and methodology development $ v k; ]! Q; \. d0 T+ k
2) Design tools/script development to improve design automation and productivity ! ` q4 f8 Y2 A) q3) EDA tools evaluation, license set up and upgrade 4 g: @- @: ^9 {: W3 l7 E0 b T+ l
4) Work with EDA vendors to solve design flow or tool issues # c: |$ ?7 C, [' W$ }4 F) n# T
5) Design database management and maintenance / w* Y$ |$ m5 o6) Local engineers working environment support and Linux/Unix servers/system support- @& D) {3 N. B4 K) Q
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Qualifications: * l9 h- u+ n+ f' W* k, C
- Experience on CAD support for digital/analog/mixed-signal IC design . [# B8 ?9 Z! v2 }9 ^% x- Familiar with IC design flow related EDA tools (Synopsys, Cadence Mentor, etc.) setup under Linux environment : s8 ~! L; K1 f1 F- Working experience in license set up for EDA tools, version control tools and bug trace tools ' L$ Q0 a9 I+ C4 Q+ T
- Excellent script languages skills for internal tool development, such as Perl, Tcl, Shell, Skill and Python9 c7 g' V. g# O& t: I
- Experience in Pcell development is a plus ) Z% u5 Z% _5 o2 o, ~
- Customer oriented, good communication skill . V& c" q/ {! Q `+ Y
- B.S. Degree or above in Electrical Engineering or Computer Science. Major in Microelectronics is a plus. / m0 \& u) ^- ] ]- At least 3-5 years CAD experience in IC design company |! H5 ^) t7 s7 w' ~- English language skill in writing and speaking.作者: ranica 時間: 2013-7-23 02:14 PM
CAD Engineer 4 m5 k7 j6 I% y9 M7 S: E1 W2 n. X4 ^" f0 e: Z
公 司：IC设计公司 1 x0 E4 m0 ~: E( ]* [: O工作地点：深圳" B4 o* y0 T4 z1 W$ x4 @
, j* r* b3 _1 j. E! wResponsibilities: ) {' `' c8 p8 ]: J' B0 w' ~1) Provide support and trouble-shooting to designers for EDA tools. & h% o8 o5 J8 C* X* M/ O6 X
2) Help to construct customed in-house analog and layout design flow ! n& G4 u$ `7 ]( O3) Maintain and 修改 EDA tools for analog and layout design. 8 o2 H+ a! x$ m, {% h4) Help designers to use new features in EDA tools, or new EDA tools. : w! f8 G6 E# U8 N9 M) {$ ]5)Maintenance of PDK and all design librarise 0 Q" k* a! ?+ a2 x8 \; h- H B# c
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Requirements: # T5 L3 z8 N9 b9 t( E1) At least 2 years of CAD or IC design relative work experience. $ a! V8 s0 e3 E# @
2) Capable of using C language, Cadence Skill language and Perl. . z, x1 U* w% C$ B3) Familiar with EDA tools including Hsim/Hspice/Spectre, Virtuoso and Calibre. / S: B+ J8 `4 P! p
4) Familiar with analog and layout design flow. 3 f0 W1 Y- |- k3 _5) Familiar with SOC design flow is a plus. ( n5 q5 u' m, j" l7 a% ? q3 r6) Experience of circuit design or layout design is a plus.作者: ranica 時間: 2013-8-29 10:01 AM
CAD Engineer [系统编号：79171319589], m+ @' p; I! d
; ?3 P8 n, y/ a7 {Job Description: $ c4 I) ?1 h. H# P$ r( }3 y9 C
Collaborate with *** CAD teams to develop industry leading design flows and methodologies for analog and mixed-signal designs using nanometer technologies, with emphasis on improvement of layout productivity of analog circuits, including usage of advanced Cadence IC6.1 features, design for manufacturing (DFM), metal fill, physical verification and tapeout flows. Write scripts and utilities to enhance these design flows. Provide CAD support and methodology training to *** design and layout community. Write application notes and document ***’s analog/mixed-signal CAD flows. Work with EDA vendors to drive ***’s interest with regard to analog/mixed-signal tools.) N# N% _0 d: U" ~ ]! d) r
/ m) E( Z% A- qQualifications: . P" R) T) S5 U$ g8 K# c9 x
- BSEE or above, with 3~5 years relevant industry experience. # J5 z2 v/ j) O( r
- Solid understanding of advanced semiconductor process technologies * n0 e: n" J1 q8 y- y/ h
- In depth familiarity with layout of analog and mixed signal circuits including knowledge of layout effects (i.e. matching, reliability etc.) and DFM rules for advanced technology nodes ( _* e8 Z' O$ p2 l$ M: ]+ @- Understanding of nanometer design rules and physical verification runsets + Q8 G {8 z4 d2 v# A) D6 B
- Solid knowledge of Cadence DFII 0 H' R# ~3 { h9 x- Knowledge of physical verification tools like Mentor Graphics’ Calibre ' ^4 X; X3 W* g) S6 u$ E. ?
- Knowledge of Skill, perl or other programming languages , B" B6 C/ E- c) e- L
- Strong written and verbal communication skills作者: ranica 時間: 2013-12-12 09:13 AM
Principal AMS Physical design engineer3 N8 f0 {4 ]: e# d+ D
公 司：One world top EDA company 1 j$ l0 l! w% W工作地点：上海 5 b- @2 D6 X& n! h; g0 B, N; _3 h$ f& g: F
职位描述7 |) O9 y, _( H$ L8 G+ O6 r2 g
Skillful capable of physical design of Analog and mixed signal area: Matching sense from transistor, Resistor and capacitor, Power and Ground coupling, Signal path from Differential pairs, etc, if knowledge on digital blocks P&R prefered.. \/ w' x! m% `: B6 i
In-depth knowledge and hands-on experience on AMS CAD support, such as write Scrips to support PDK(pcell, call back), ams back-end stuffs, including Skill language, Perl, verification runset improvement etc 4 M$ O( c" A. NProficient with xx layout tools specifically Virtuoso XL and Assura (xx 6.1 experience a plus) , ~2 A. }+ G6 U4 u& E3 |' oExperience in 65 nm and below analog CMOS layout, verification (DRC, LVS), and top integrated tapeout to foundry/ H% T* _6 t* t/ D
Ability to coordinate with the other analog IC circuit layout, ensuring robust, efficient, consistent and successful delivery of analog IC circuit layout., t5 s5 ~0 b+ g7 |/ {
Fundamental understanding of IC design technology and process/methodology : j1 a" `# a; E3 xSkilled in Analog IC top level chip assembly including floorplanning and block layout 6 a, [/ H( F9 n# y* v) Pedicated experience on key macros is prefered: SerDes, High speed/high resolution Data Converters; High Speed PLL''s; Low Noise Design; 5 o* f, h# T% U7 a/ ~
Hands-on experience conducting DRC/LVS analysis and recommending appropriate solutions , K6 ~+ N- X+ T. e
Solid understanding of IC design technology and process/methodology in AMS layout 3 l8 H) i+ G$ {2 i0 k2 R% q. R 1 t+ y1 j/ @# e! x. iPosition Requirements: * ~, q. M5 \! S/ P BSEE degree with >6+ years of applicable experience in advanced analog and mixed signal design industry. Essential that the individual demonstrates strong communication, verbal and written, and project management skills. Requires very good communication skills in English and Chinese.4 U( L6 [! b* s' g
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Company Info Type: # N3 b) V$ p, X5 ~0 J( Q
Global Default 0 a8 S; \( c; f+ u: T; ^
% G9 z7 h4 `# J: K! V; s7 _8 N7 }Company Information: , E1 [+ W! z8 J8 }9 \9 I& X4 T9 d' ^$ a/ G
xx is the global leader in software, hardware, and silicon IPs that is driving the transformation of the electronic design automation (EDA) industry. This application-driven approach for creating, integrating, and optimizing designs helps customers realize Analog & Digital ICs , System-On-Chip devices, IP and complete systems at lower costs and with higher quality.作者: ranica 時間: 2014-1-23 08:55 AM
Senior/Staff DFT Design Engineer ! e1 I5 ^, V. p5 d公 司：A famous IC company8 M$ ^; ?( j0 P2 b7 F' K& j
工作地点：上海 5 v' \2 O( z: l# z& u 9 Y, ] |* R9 W1 e; Z; o! bDescription: $ z; U8 R7 Y$ h8 p( A7 H0 T- Block, IP and SoC level DFT implementation (bscan, scan, mbist, jtab, analog test structure, etc.) ' ]' P- _, H: x" B; L$ w- work with IP vendor (internal/external) to analyze DFT integation issues 3 X' K( L, ?4 n5 a( I6 F* Z r9 l* k3 c- DFT STA, constraint generation, formal and timing closure 2 w9 M- x) B$ ~$ C& `0 N- DFT flow development and maintenance * [( n+ \$ _3 h- test vectors generation and verification 3 V' u! p% }1 x0 o- interface to backend team on physical design and timing closure ( i! A e8 a: a% \) o. k% {* h# w
- interface to test engineers on ATE and vectors bring-up and debug , Q* {( V, f! i) J' e0 G
- chip DFT quality sign-off3 J4 a3 n( y& S- {3 l
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Qualifications: " I! n( Z7 o% G ~4 g! J# aMust have: ! _( H; [5 e) ?! N! X! a+ j
- minimum 4+/8+ years of DFT design and integration experience " g1 u: d% j' v: |! Q+ r: V- hands on DFT implementation experience (bscan, mbist, scan, IP testablity integration, at-speed & _: p) f0 L1 m' G
scan, IDDQ test, ATPG and fault simulation) 2 E& v* i1 H% f6 q' w1 s c3 I
- expertise with DFT tools from Synopsy, Mentor, Syntest and Logic Vision ; N3 O6 G- L$ I% `- d3 \- strong logic design and verification backgroud solid experience in STA % a4 L! p4 H3 W% ?! `; r" J- proficient in Perl, tcl and shell programming % {5 @$ l. S9 O3 n
- BSEE degree or above 3 j4 Y9 u+ I* Y- ] `- good team work spirit / s: v7 }; O! A# i0 p2 }/ h$ y# @: Q
4 X3 c5 m$ R2 }3 R# g% p( pNice to have: 0 H# {0 x% z8 T# c% n- familiar with DTV/STB architecture, design, and IP 7 q" H; `# b3 C5 j. f0 X- proficient in C++ and system verilog作者: globe0968 時間: 2014-2-14 02:04 PM
Principle SI/PI Engineer 6 n# |) N' \1 D& y3 o/ r公 司：One world top EDA company. F5 G# \" i3 F
工作地点：上海5 W6 t" M) t* D9 A+ s. d/ _6 E
4 m- [: z1 C% q( e# N# M+ L0 ~! e" PPosition Description: 9 E3 F8 |! v1 j1 N( _$ @
Complete power-delivery system analyses across chips, packages and boards. System-level SI analysis, including simultaneous switching noise analysis of high-speed signal transmissions, and advances physical design for single- and multi-chip packages, states-of-the-art 3D packages, and systems in packaged (SiP). The engineer should be able to act as a strong team member and contributor. ' f* w" i! N, i0 Y0 e. j 6 @3 |9 g2 @; H4 WSpecific duties include: & C: M$ }( @7 u7 D }& H# V
- Be responsible for building SI/PI/SiP design flow for High-speed IP Design 8 c8 f7 J# A# Z" ~( u
- Proficiency in Cadence tools: Allegro and Sigrity $ Y, [0 |6 C. }1 ^
- Proficiency in Hspice or spectre simulation, especially in high-speed simulation. ! S+ o2 c1 _2 d1 R: Z& I7 d- Good knowledge in modeling, for example IBIS. " Y' |& \. A8 G! f0 ?- Good knowledge in high-speed PCB design. 3 N$ u4 [8 s ^+ B* p- At least eight years experience focus on SiP and SI/PI analysis, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment is required. 0 @; g4 }1 @. a3 Y0 r6 f/ |2 E J- L) S
Position requirements: 1 Z0 ]2 ?7 _( H& S5 x1 F! BEssential Qualifications: 2 S: ]8 L! U5 u9 r* j1. Must have BS degree with 10+ years of applicable experience, MS degree with 7+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics. : K) W" C; N4 ~8 \
2. Essential that the individual demonstrates strong communication, verbal and written. Requires good communication skills in English.8 r, S; j3 p) ~! M5 {
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Desirable Qualifications: 9 s! x/ s( T; V# i2 Q: r
A minimum of seven years relevant experience in industry. ( o- G. L' B1 i
- At least five years experience driving SiP/PI/SI project. 9 I8 h3 f; s( H. K5 X2 w
- Will have demonstrated successful completion of 10+ projects as an individual contributor作者: ranica 時間: 2014-5-21 09:33 AM
DIP Application Engineer 5 C; F# v" w3 _9 Y# D6 I6 S S q: i公 司：One world top EDA company ; k4 f- F5 k2 f- M7 B3 D工作地点：上海 + p. n9 V& d" t8 M7 x " ]0 Z' O' k4 TResponsibilities: . B8 `9 R: N- k4 w5 T1) Providing direct technical support to customers in presale stage to persuade customers to adopt Cadence Design IP solutions for their applications ' x+ X* W; i( Z7 f9 ^9 X2) Interface with customer architects and Design IP business unit to enable evaluation of application specific IP performance and features per customer’s SOC requirements.* ~3 E' M- C; L- H0 d3 a
2) Working with the sales team to manage the IP activities in the region to achieve a high customer satisfaction rate and for building strong customer relationships ( M' A) T Z0 u' J+ L5 J3) Providing customer feedback on new/existing requirements for Design IP usage from customers to the IP business unit.& ]* i$ q4 w) l
4) Providing direct technical customer support and assistance to enable customers to successfully integrate/use Design IP in their SOC. ( t; G# S2 b+ | u" j5) Writing application notes in situation to facilitate customer usage of the IP 9 f3 z7 Q2 K' F( j1 M$ k6 z" k0 b- R$ ]* P) e: ]7 C
Position Requirements : 0 r/ |4 X( k4 [! q h1) Experience in digital/analog design and implementation of controllers/phy 1 j$ ^2 A' E. j. Q' [
2) Knowledge of serdes and backend implementation is a plus 2 ^, W$ j% b/ Q/ N& x$ t4 n& b; G9 }- _
3) Experience with SOC architecture include on-chip fabric (AMBA/Sonics OCP/Arteris NOC), external interconnect protocols (e.g PCIe/Ethernet) and DRAM memory protocols (DDRn, LPDDRn), DRAM PHYs, .NAND Flash (Async, ONFI, Toggle NAND), eMMC/SD, MIPI ) @0 Q8 {9 ]1 G4) Knowing serdes/analog IP is a plus 0 k! k: ?2 b" c; b1 s2 K* L6 C
5) Exposure to IP-based SOC design flow and real tape-out experience. , Q5 Z4 m% z/ j5 N4 g: _( N/ O6) Good written and verbal communication skills and problem solving skills are required. 0 t5 I: Q6 d' @ } Y7) Ability to conduct technical meetings, presentations, seminars and training to customers and to the sales team : `, m$ m. ~7 E5 B2 {" J9 n8) Travel within AP region may be required. % H+ K& M8 X& E6 g* ?9 k) H6 Q9) Good understanding of the semiconductor IP marketplace and ecosystem is a plus.作者: ranica 時間: 2014-7-29 11:21 AM
Senior Engineering Manager & t; Z! j- V! B) w ! z+ b' O/ W ^3 Y* T公 司：One world top EDA company6 f5 C) N2 j% f
工作地点：北京3 F1 k! J+ j, e1 I9 [+ g
8 U7 A$ {# x; d0 g
Position Description . y, m2 @: e) X8 |/ a( Z Z% {1. World’s leading design companies rely on xx technologies to deliver the latest design innovations in consumer, 6 G* Z5 Y' M% Lmobile and enterprise electronics. We are looking for a strong software engineering leader to join our team and contribute to the continued growth and success of the company’s flagship products, including ADE and AMS Designer. 6 Y$ Z9 a! \' L7 a k! M3 B2. In this high-impact career opportunity you will be responsible for delivery of cutting-edge features in mixed-signal simulation and the Virtuoso environment, including technology leadership, team development and people management. + q$ ?5 G! |; L9 {+ y* u" ~1 Z& I& B3. You will also work with a cross-functional team in Beijing and North America to ensure that our software is developed, tested, and documented with high quality. ~6 R# b2 p+ y0 y' j- u
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Position Requirements / m( \/ N, P- c5 p$ Q# E
Requirements: : [* y( L$ y2 F$ N! S1. Experience managing software development teams in the EDA or related industry ; i+ s+ A) E9 D( i3 n1 W2. Successful delivery of software products over multiple release cycles : x' } f8 ^! d @" Q9 n* B1 z* l2 j3. Proficiency with build and version-control systems ! _/ [1 c j# B8 ~: H3 S7 @
4. Strong software engineering skills in C/C++ and familiarity with Linux/Unix development 6 N" }( i) Q: i$ Y. G# [3 D
5. Excellent written and oral English communication skills 7 v2 l! W" o q6 e U) @( H
+ y1 h. r6 {6 j! B
Preferred skills: 4 M" F9 t' D) n1 T2 \/ e
1. Prior experience with analog, digital or mixed-signal simulation using SPICE, Spectre and Verilog languages 1 H9 Z$ h, g) U! ^/ m% Z2. Exposure to the Virtuoso environment or other electronic design platforms / c8 D' G X- U# n L & Y2 T# D4 k9 s: FEducation: # W: ~4 \& m. S- _+ E( YB.S. or higher in engineering, computer science or related field.
