5 |) J3 `7 {* c(台北訊) 全球半導體設計製造軟體暨IP領導廠商新思科技(Synopsys)近日宣布,針對SoC設計推出完整且經軟硬體整合之音頻IP次系統─DesignWare® SoundWave音頻次系統。該解決方案不但可完全配置(fully configurable),且支援2.0至7.1音頻串流(audio stream)並具備24位元精準度,可有效支援數位電視、機上盒、藍光光碟、可攜式音頻裝置及平板電腦等廣泛音頻應用的要求。作者: mister_liu 時間: 2012-4-16 04:10 PM
SoundWave音頻次系統的元件包括:DesignWare ARC®32位元音頻處理器、標準數位介面、類比編解碼(analog codec)、支援最新杜比(Dolby)、DTS及SRS格式的完整軟體音頻編解碼庫,以及包含媒體串流整合架構的完整軟體環境。此外,該音頻次系統亦兼具虛擬及FPGA原型建造(prototype)的功能,能協助設計團隊加速軟體開發及全系統(full system)的有效性確認(validation)。新思科技所提供之SoC就緒的音頻解決方案,可將多重IP區塊(block)與軟體整合並預先經過驗證(pre-verified),大幅縮短SoC設計及整合過程、降低設計風險並加速上市時程。4 K5 R0 ^7 E- R$ r5 G) F7 J
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隨著多重音頻內容的使用增加以及音頻應用的取樣(sampling)比例提高,消費性應用SoC的複雜度也隨之提升。再者,新的音頻規格要求更多訊號處理及頻寬,以期在各式音頻格式上達到高品質的聲音重現(sound reproduction)。使用專門的音頻次系統能將主處理器的音頻處理工作釋放出來,如此可降低設計的複雜度,並提升SoC的效能及效率。 3 C" h/ ?2 s: i* P : ^+ W( M- L% m+ P市場研究機構Semico Research公司資深市場分析師Rich Wawrzyniak表示:「預計在2014年以前,每個SoC的平均IP區塊(IP blocks)數量將達到120個,因此設計人員需要一套能協助他們縮短整合IP過程以及管理這些複雜區塊的解決方案。透過一個涵蓋軟硬體且經過預先驗證的完整IP次系統,設計人員無需在個別區塊層級(individual block level)而是在晶片層級(chip-level)就能解決設計問題。藉由推出DesignWare SoundWave音頻次系統,新思科技不僅在IP產業開創了新局,也將加速電子產品開發人員的創新速度。」作者: mister_liu 時間: 2012-4-16 04:10 PM
整合硬體 (Integrated Hardware) Z5 [+ w) c$ i ) r6 N) Z1 R& ~' A7 N) TSoundWave音頻次系統提供功耗效率佳的ARC單核心或雙核心32位元音頻處理器選擇,可同時處理多重高傳真(high-definition)及多重頻道(multi-channel)之音頻串流。該次系統包含支援晶片外(off-chip)音頻傳輸連結的數位I2S及S/PDIF介面,以及HDMI介面的高頻寬晶片內(on-chip)傳輸連結。ARM® AMBA® 3 AXI™/AHB協定系統介面(protocol system interfaces)簡化了整合至SoC架構的過程。/ a; \4 {5 ]* T9 J
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類比音頻編解碼為線性輸入(line input)及輸出(output)、麥克風、擴音喇叭、耳機提供高品質的音頻傳輸連結。易於使用的配置工具讓設計人員能快速選擇頻道及音訊介面的數量,使得以往利用手動需耗時數周的完整音頻次系統配置能在數小時內完成。此外,新思科技也提供SoC整合服務,協助客戶將次系統整合至晶片中,或是透過客製化達成特殊應用需求。 1 S5 t' U) [. u. ]# C( i
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專用軟體 (Dedicated Software) . v- K n% G: e5 I* A# k. v5 {+ P3 H: g5 M
SoundWave音頻次系統提供完整且可立即使用的軟體環境,其中包括支援最新的多頻音訊格式(如杜比的Dolby Digital Plus和TrueHD、DTS的HD Master Audio、SRS的TruSurround HD4和TruVolume和微軟的WMA 10 Pro)以及熱門的開放原始碼音訊格式(如Ogg Vorbis和FLAC)的音頻編解碼。作者: mister_liu 時間: 2012-4-16 04:10 PM
SoundWave音頻次系統的整合媒體串流架構含有編解碼器以及聲量控制、等化處理(equalization)、環繞平衡(surround balance)等音頻後處理功能,該架構允許軟體編解碼及後處理軟體易於次系統中進行實例化;此外,根據產業標準GStreamer多媒體軟體所開發的音頻插件(plug-in),能讓設計人員快速將音頻次系統軟體整合至主應用軟體(host application software)中。 3 C0 H" F' ?+ a" R* u$ t
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虛擬及硬體的原型建造 (Virtual and Hardware Prototypes)% P! Z% Z1 f* h# G
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在開發軟體內容豐富的電子裝置時(特別是針對行動及消費性電子產品),設計人員不但需要將日益多樣的軟體內容納入設計考量,還必須面對軟體開發以及軟硬體整合的挑戰。為了縮短軟體開發的時間,新思科技SoundWave 音頻次系統的Virtualizer™虛擬原型建造,可協助設計人員在矽晶產出的數月前便能進行音頻軟體與應用軟體的整合。該音頻次系統的HAPS® FPGA原型建造解決方案可達成快速的軟體開發,並為全系統整合及驗證提供可擴展的平台(scalable platform)。 6 A7 m3 L6 ]6 h" |! d
) o4 O6 V) _9 K2 e/ q0 {; T5 T新思科技IP及系統行銷副總裁John Koeter表示:「設計人員不斷調整方法以因應日益複雜的SoC設計,IP解決方案也需跟著精進。軟硬體的最佳結合能有效支援設計上對效能、成本、功耗及時程的需求。DesignWare SoundWave音頻次系統提供預先驗證的完整端對端(end-to-end)音頻次系統,協助設計人員大幅縮短概念(concept)到實作(implementation)的時程。」作者: amatom 時間: 2012-6-19 11:27 AM
Imagination Optimizes its IP Capabilities with TSMC on Latest Silicon Process Technologies* G2 R* S( K; U2 R$ q; N) l
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Imagination Technologies, a leading multimedia and communications technologies company, announced its collaboration with TSMC to ensure that licensees of all of Imagination’s IP (intellectual property) cores can optimize speed, area and power consumption on TSMC’s most advanced 28nm and below processes. $ }+ P4 }0 t' ~( z 5 j8 U* V$ Z# V; [; oBy bringing together engineers from both companies, this collaboration aims to improve power, performance, and area by co-optimising TSMC process technologies and foundation IPs with Imagination’s most advanced IP cores, including its latest PowerVR GPUs. , |3 V6 y% w6 U! A! d1 l
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Imagination, a member of TSMC’s Soft-IP Alliance program, is making this announcement as part of a closer relationship with TSMC. Imagination intends to validate its IP cores through the TSMC Soft-IP Alliance program.作者: amatom 時間: 2012-6-19 11:49 AM
Imagination’s IP core families in this collaboration include:7 x i K2 |7 n1 i/ r
, i$ @( x: K; e$ Y6 l& _•PowerVR graphics, the de facto standard for mobile, embedded and computing graphics 3 L" N, o7 n- ]7 F: F% j•PowerVR video and display, the comprehensive and widely adopted range of multistandard decoder, encoder and enhancement cores for applications from mobile to ultra-HD 5 s. a1 s/ z% X8 p•Ensigma communications, the multi-standard programmable communications and connectivity technology for TV, radio, Wi-Fi and Bluetooth! |* W- \- F+ w, V+ K+ H6 J+ ]
•Meta processors, the advanced 32-bit hardware multi-threaded processor architecture that delivers the best in both general purpose and signal processing performance - N; T7 O& c( m8 J) {/ A0 @ ( t( x, n- T7 ^2 d# D3 e& `Imagination is one of the world’s leading semiconductor IP suppliers, with cores which can be synthesised for a broad range of silicon processes. As more customers use Imagination’s IP cores to deliver the key high performance processing on their SoCs (System on Chip), Imagination plays a key role in the semiconductor IP segment to deliver the levels of performance demanded by leading edge customers.作者: amatom 時間: 2012-6-19 11:49 AM
Says Tony King-Smith, VP marketing, Imagination: “Many of our licensees rely on TSMC to provide them with leading edge low power, high performance silicon foundry capabilities. This strengthening of our relationship with TSMC reflects our determination to deliver the best possible SoC solutions on the latest silicon processes for our SoC IP licensing partners. We believe this initiative will ensure that Imagination’s licensees to continue to push the boundaries of what is possible for future generations of advanced SoCs.”: ?/ B3 n& w/ R# o C. {7 n
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Says Mark Dunn, VP of IMGWorks, Imagination’s SoC implementation group: “The characteristics of the latest processes such as 28HPM and beyond have to be taken increasingly into account when designing future high performance IP-based solutions. As major blocks such as GPUs increasingly dominate the area, power and performance of next generation SoCs, design flows need to be tuned to maintain the optimum balance between maximizing IP portability and achieving the best possible performance. We believe this extensive engineering partnership will greatly benefit all of our IP partners.” , i z3 z1 m' j5 ~# s" q: _" W& ~0 J) ^
“We are delighted to be working with Imagination to deliver the full benefits of TSMC’s latest and most advanced processes for mobile and embedded applications,” says Suk Lee, Senior Director of Design Infrastructure Marketing Division, TSMC. “By leveraging Imagination’s leadership position in the market, we can help our customers to ship the most highly optimised SoCs.”作者: innoing123 時間: 2013-4-16 03:23 PM 標題: 聯芯採用Hantro視頻IP產品 全球基於Hantro視頻IP的芯片出貨總數已超過10億顆6 q; n! A& y9 f/ {
& o2 K, D6 d7 c5 p6 i+ [- m- LGoogle 正積極向業界推廣名為 WebM 的免費、開放的媒體文件格式。芯原作為 WebM 生態系統的合作夥伴,可向全世界範圍內的半導體廠商商業授權 Hantro G1 多格式解碼器和 Hantro H1 多格式編碼器 IP,並有權修改 Hantro 視頻 IP 以加強內核架構和增加新功能等。目前,Hantro 視頻 IP 已獲得全球範圍內70多家半導體廠商的採用,基於該 IP 的芯片出貨總量已經超過10億顆。 ; ?( M9 m, Z) T! h
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「Hantro 視頻 IP 使得我們的產品在具備出色的視頻性能的同時,還兼顧了功率和成本效益。我們感謝芯原在合作中所展示出的優秀的專業技術實力和客戶支持能力。」聯芯副總裁劉積堂表示,「我們的產品可支持包括 VP8 在內的多種視頻格式,並已被許多知名的智能手機和平板電腦品牌廠商所採用。」作者: mister_liu 時間: 2013-5-22 02:27 PM
Principal Product Engineer-----DDR IP & W5 @% m) u0 x2 T. ^公 司:NO.73-One world top EDA company( W. ~" |2 i; l7 I9 I0 u
工作地点:上海/ x X7 X+ X0 J5 @! v
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Position Description: $ e, ~4 z) Q- g& B' y' i# \* b/ h/ rOur client is looking for an individual to work in design IP team. The group provides configurable DDR memory controller and PHY IP for ASICs. The job will be mainly focused on providing post technical support to customers; however there will be a variety of other engineering tasks that will allow the candidate to expand skills and responsibilities. . _0 F o9 o$ W; z t ; q) I3 w& o# v2 zProvide technical support to customers for integration of IP into ASICs including: / M* n# g4 L# C w3 W: q* p- Debugging of customers’ simulation or silicon issues. : G7 v8 {2 S V
- Reviewing of customers’ design integration of our IPs.( x; G5 B! J8 S, j2 ~: P
- Reviewing static timing reports to assist with customers’ timing closure. * e0 C' K, J1 M: A4 O- Answering technical questions about IP operation. ; h. m' Z$ O( a+ q6 i! ~- |5 d. ?' {
- Train field engineers in IP operation. ) u9 J9 ?/ T4 p" s. G6 ]" T- Interface with the R&D Team to bridge product improvements and resolve customer issues. + k6 g' a9 A, M. [5 Z+ J$ D# m+ Y' P' p- \7 [# @, A2 p" J
Position Requirements: . h. J) n. |8 l( U+ w6 ]# \& z
- Excellent oral and written communication / j& d0 z7 i$ L& J* b1 V' W- Good English communication skill, O5 N" c! l+ u$ y% {! k
- BS 8+ years of prior work-experience or MS 6+ years of prior work-experience7 {# A+ {( f% Y- i9 _0 f9 ?
- All front-end skills – RTL design & verification in Verilog, synthesis, static-timing analysis, DFT3 c& u" C( E! W. p1 c, J
- Back-end skills – place & route, physical verification, timing closure) V/ B+ ?- ~" k3 m
- Time management skills sufficient to balance multiple high-priority projects.+ [0 g$ E4 J5 Y! k v# K
- Willingness to learn new skills and perform tasks that often go outside area of current expertise. * u* K( u7 g- f) k% ?. `* X0 K2 F8 C$ j2 J+ P" w* m
Additional Desirable Qualifications:9 P! M! N) o; `9 Y, [- W% T
- Experience with Static Timing scripts and report analysis / n1 M+ }( W8 ]' j- Familiarity with DDR memory operation, system applications, AXI, OCP, AHB 9 C" ^) ?; b. N7 N( I( N- Familiarity with Frame maker ' ?) a9 ]" c6 V0 g3 c; @' L: d- Scripting – in Perl, TCL, etc..作者: tk02376 時間: 2013-5-23 04:23 PM 標題: Imagination:第三方IP成為推動半導體業者發展的重要力量 [attach]18381[/attach] : W& H: {3 K3 o5 t- |Imagination可為SoC所有重要功能模塊提供IP解決方案- d7 c5 ]* c/ }) @: d# z
; F. Y4 f2 X, S5 }(台北訊) 隨著半導體製程進展到28/20奈米世代,製造與設計能力間的落差也越來越大。晶片設計人員為了能在最短時間內將更多樣的功能整合到系統單晶片(SoC)中,採用第三方業者提供的矽智財(SIP),而非自行開發,已逐漸成為一種趨勢。透過運用高品質、完整的第三方IP解決方案,晶片設計人員能將資源專注於開發具差異化特性的產品,包括連結各種IP模塊的設計方式。因此,這已使得SIP市場近年來成長的快速。8 G4 w% E2 }7 F$ N
$ R6 p: r3 K; ]* r$ U$ {1 _6 ]根據研究機構Markets and Markets發佈的數據,全球SIP市場營收預計將從2012年的25億美元到2017年成長到57億美元,年複合成長率(CAGR)達14.5%。特別是,在行動裝置、各類消費性電子創新設計帶動下,處理器IP市場的漲勢最高,達21.2%,表現優於整體市場。作者: tk02376 時間: 2013-5-23 04:23 PM
而在處理器IP中,GPU(繪圖處理器) IP由於具備平行處理特性,有更佳的可擴充性,已成為近來推動行動SoC效能提升的重要力量。此外,結合CPU與GPU的異質運算架構,也將能夠進一步提升效能與降低功率,將能為新一代SoC設計開啟全新機會。 9 @6 m; F1 K. g5 s8 D! ^7 l! Z/ L9 U+ R) B( g
全球前20大的領先半導體與OEM業者,包括英特爾、聯發科、Sony、三星等知名業者都是採用第三方業者提供的矽智財(SIP),將其技術應用於行動電話、平板電腦、電視、機上盒和車用電子等各消費性電子產品中。此外,藉由適當的結合IP技術,半導體業者便能推動智慧型手機與平板電腦的創新設計,開發出令人驚艷的使用者介面與繪圖功能。 2 ?4 `' i+ ^* D+ ^
! w) g2 G6 w u0 r; i$ `此外,Imagination在今年初併購MIPS後,強化了其既有的CPU IP產品組合。Imagination原本就已積極開發CPU技術,納入MIPS後,將更能加速此計畫的實現。這項併購行動有助於公司提供完整的領先IP解決方案,以滿足新一代消費裝置的設計需求。 ' U$ ^# S2 M, [( S+ S L/ q! ?1 Z& B7 V# \! L! y9 o看好台灣市場的發展潛力,Imagination自去年(2012年)首度在新竹舉行技術論壇獲得熱烈迴響後,今年(2013年)更將擴大舉行,預計於6月26日和6月28日兩天分別在新竹、台北兩地進行IMAGINATION高峰論壇。這是Imagination在併購MIPS後首度舉辦的技術論壇,開發人員將能全方位瞭解Imagination與MIPS結合後的完整技術方案以及最新的SoC設計趨勢,並特別邀請到Imagination的重要生態夥伴成員發表專題演講。請千萬不要錯過了我們為本地開發人員精心安排的一整天精彩活動! & t+ P1 R$ T/ W) M# T / _% Q3 ?3 ]* K6 V( c- E【活動資訊】 ; r# p- e- j9 ^- P1 ]活動日期、地點:1 O$ B! I: m+ Q6 a7 ^
l 新竹場6月26日新竹喜來登大飯店(新竹縣竹北市光明六路東1段265號)2 p0 F' @% c- W# g, X
l 台北場6月28日台北六福皇宮(台北市南京東路三段133號)作者: ranica 時間: 2013-6-13 10:57 AM
Principal Product Engineer-----DDR IP# C' |7 j% f" m% }. N% D
公 司:NO.73-One world top EDA company8 o2 \# h' z1 v) r0 A
工作地点:上海5 k" x! z5 ?) \, c' m
, m1 Q3 t0 y- }* C# z, B
Position Description: 9 z! O: ~1 ?+ t$ P0 N* G) F9 g5 mOur client is looking for an individual to work in design IP team. The group provides configurable DDR memory controller and PHY IP for ASICs. The job will be mainly focused on providing post technical support to customers; however there will be a variety of other engineering tasks that will allow the candidate to expand skills and responsibilities. * d. |) J8 g9 ^) }* f( f; p " @4 Q7 K4 t+ J: ?1 N' A | GProvide technical support to customers for integration of IP into ASICs including: 4 {3 _- K3 O X1 L; M# a1 M( J
- Debugging of customers’ simulation or silicon issues. ! P' r; ~6 A2 m0 A0 L
- Reviewing of customers’ design integration of our IPs. / K: s/ u9 Q, h/ K! O' Q& d- Reviewing static timing reports to assist with customers’ timing closure. 5 I7 m$ f2 U8 N" R. t' @
- Answering technical questions about IP operation. 4 m0 f1 a" d5 P; x2 i& {4 j s- Train field engineers in IP operation. ) z. C5 N) O/ ? t/ G3 l) r- Interface with the R&D Team to bridge product improvements and resolve customer issues./ E4 T. j c7 h/ f* i7 E/ |3 ?
9 q$ I- m2 l* S* i8 XPosition Requirements: ( f w" M/ E1 e/ r. d* l- Excellent oral and written communication 0 C! n, q1 K3 K& n2 B( k9 p3 W
- Good English communication skill 1 p$ U# G& e0 q
- BS 8+ years of prior work-experience or MS 6+ years of prior work-experience ! X5 `2 r" b- B! ]8 \) Q8 w
- All front-end skills – RTL design & verification in Verilog, synthesis, static-timing analysis, DFT 0 K. w8 Y3 Q9 x$ Q6 n% p
- Back-end skills – place & route, physical verification, timing closure & `2 j1 W8 A/ ^# P' m) x& z E- Time management skills sufficient to balance multiple high-priority projects. 5 g9 }) T' k6 j& e# s
- Willingness to learn new skills and perform tasks that often go outside area of current expertise. 5 g4 L* W# v0 f* T/ Q4 g' e 2 r2 \) G! C3 f/ b0 @/ I- z
Additional Desirable Qualifications: 7 l$ q& G' T4 Y; B/ b
- Experience with Static Timing scripts and report analysis ( B8 ]1 y( W' v& J1 F% T0 `; p8 ]- Familiarity with DDR memory operation, system applications, AXI, OCP, AHB % ~( G" ? z& S+ y1 b1 {% _- Familiarity with Frame maker , W: T) i2 }2 z' p
- Scripting – in Perl, TCL, etc..作者: sophiew 時間: 2013-7-2 09:44 AM 標題: 芯原發佈支持HEVC和VP9的Hantro G2視頻解碼IP 全球首款同時支持HEVC和VP9視頻格式的半導體IP 1 W' j8 F: Y9 m0 Q: \( _# Q' b. |7 E$ }
上海2013年7月1日電 /美通社/ -- 為客戶提供定制化芯片解決方案和半導體IP的世界領先的IC設計代工公司芯原股份有限公司(芯原)今天宣佈推出Hantro G2多格式視頻解碼IP,支持高效率視頻編碼(High Efficiency Video Coding,簡稱HEVC或H.265)標準下的超高清4K視頻解碼,以及 WebM項目下即將推出的VP9網絡視頻格式。此外,Hantro G2 IP還支持包括H.264、VP8、MPEG-4、VC-1、AVS(即將支持AVS+)、MPEG-2、DivX、Sorenson Spark和VP6在內的其他多種視頻格式。 , B, x) g3 l# k