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標題: STD Cell Data Prepare 中 wire track 的問題? [打印本頁]
作者: hgby2209    時間: 2007-1-17 09:16 AM
標題: STD Cell Data Prepare 中 wire track 的問題?
Standard Cell 的 Data Prepare 的過程我會去做 axgDefineWireTracks
* l& h- u6 U, M然後再做 axgCheckWireTrack 來 check wire track, 但是做完 axgCheckWireTrack  * P  F8 A4 H+ _7 H! e! p# |
之後卻有如下之 Meaasge:
/ W8 R& d+ A6 Z4 l
  o4 ^  P+ R4 b9 B. W! J  p  G******** Pin Access Analysis *******
5 X2 y, S/ t% h# l/ ^. l** # Cell Masters    =  1000% Q) M" Y+ @. w! H! ~! K
** # Ports (logical) = 2500$ v$ V5 j3 `8 r( d) J- K
** # Pins (physical) = 25005 j8 n% K1 g" N1 K' \; r0 x
** # Pins with no good access point on Grid (V&H) =   5 ( 0%)
! h, A3 i6 j( i" B( g2 W( H3 J3 N** # Pins with no good access point on Ver-Grid =    5 ( 0%). a; w8 a" M( D: x1 E3 d

( x5 Z, B7 F9 D" \7 x8 c請問下面這兩句是代表什麼意思呢?
/ [) `) i8 ]4 ~- _8 X6 T* L** # Pins with no good access point on Grid (V&H) =   5 ( 0%)+ j* X6 e) G4 B0 [9 M2 T5 B
** # Pins with no good access point on Ver-Grid =    5 ( 0%)1 v% x  a; k$ s7 V! _1 q: ]8 Z
( m1 |8 ~, w2 G0 T* i8 C
若是代表有錯誤的話是否要 Fix 呢?



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